Computer Hardware User's Guide

Overview
2-5 Architectural Overview
Figure 2–3. TMS320C32 Block Diagram
24
24
40
Destination-address register
Global-control
register
Timer0
Timer-period
register
Timer-counter
register
Timer-counter
register
Global-control
register
Serial-port
control register
Destination register
Source-address register
Transfer-counter rregister
Boot
ROM
Program
cache
(64 × 32)
RAM
block 0
(256 × 32)
RAM
block 1
(256 × 32)
IR
PC
CPU1
REG1
REG2
Multiplexer
40
32
32
32
32
32
32
32
24
24
24
BK
ARAU0 ARAU1
DISP0, IR0, IR1
Extended-
precision
registers
(R0–R7)
Auxiliary
registers
(AR0–AR7)
Other
registers
(12)
40
40
40
40
Multiplier
32-bit
barrel
shifter
ALU
External
memory
interface
Serial port
Data-transmit
register
Data-receive
register
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
TCLK0
Timer1
Timer-period
register
TCLK1
PDATA bus
PADDR bus
DDATA bus
DADDR1 bus
DADDR2 bus
DMADATA bus
40
32 24
24
24 2432 32 32
CPU2
32 32 40
Receive/transmit
(R/X) timer register
Controller
CPU1
REG1 REG2
DMAADDR bus
STRB1
control reg.
IOSTRB
control reg.
STRB1
IOSTRB
STRB0
RESET
INT(3-0)
IACK
XF(1,0)
H1
H3
MCBL / MP
CLKIN
CV
SS
(6-0)
DV
SS
(6-0)
IV
SS
(3-9)
DV
DD
(11-3)
V
DDL
(7-0)
V
SSL
(5-0)
V
SUBS
SHZ
EMU0–3
32
Multiplexer
A23 – A0
D31 – D0
R/W
RDY
HOLD
HOLDA
PRGW
STRB0_B3/A
–1
STRB0_B2/A
–2
STRB0_B1
STRB0_B0
IOSTRB
STRB1_B3/A
–1
STRB1_B2/A
–2
STRB1_B1
STRB1_B0
Source-address register
Multiplexer
Transfer-counter
Global-control register
Global-control register
DMA channel 1
DMA channel 0
DMA controller
STRB0 control reg.
Peripheral address bus
Peripheral data bus
Legend:
PDATA bus – program data bus
PADDR bus – program address bus
DDATA bus – data data bus
DADDR1 bus – data address 1 bus
DADDR2 bus – data address 2 bus