Computer Hardware User's Guide

Overview
2-4
Figure 2–2. TMS320C31 Block Diagram
32-bit
barrel
shifter
ALU
40
24
Boot
loader
Cache
(64 × 32)
RAM
block 0
(1K × 32)
RAM
block 1
(1K × 32)
RDY
HOLD
HOLDA
STRB
R/W
D31– D0
A23 – A0
RESET
IR
PC
CPU1
REG1
REG2
Multiplexer
40
32
32
32
32
32
32
32
24
24
24
24
BK
ARAU0
ARAU1
DISP0, IR0, IR1
Extended-
precision
registers
(R7–R0)
Auxiliary
registers
(AR0 – AR7)
Other
registers
(12)
40
40
40
Multiplier
DMA controller
Global-control
register
Source-address
register
Destination-
address
register
Serial port 0
Serial-port control
register
Receive/transmit
timer register
Data-transmit
register
Data-receive
register
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
Timer0
Global-control
register
Timer-period
register
Timer-counter
register
TCLK0
Timer1
Global-control
register
Timer-period
register
Timer-counter
register
TCLK1
Port Control
Primary STRB
-
control register
Transfer-
counter
register
PDATA bus
DDATA bus
DADDR1 bus
DADDR2 bus
DMADATA bus
DMAADDR bus
24
40
32
32
24
24
32
INT(3 – 0)
IACK
MCBL / MP
XF(1,0)
V
DD
(19 – 0)
V
SS
(24 – 0)
X1
X2 / CLKIN
H1
H3
EMU(3 – 0)
32 24 24
24 2432 32 32
CPU2
32 32 40 40
MUX
Controller
Peripheral Data Bus
Peripheral Address Bus
CPU1
REG1 REG2
Multiplexer
SHZ
Multiplexer
PADDR bus
Legend:
PDATA bus – program data bus
PADDR bus – program address bus
DDATA bus – data data bus
DADDR1 bus – data address 1 bus
DADDR2 bus – data address 2 bus