Computer Hardware User's Guide

Memory Access for Maximum Performance
8-23 Pipeline Operation
Table 8–2. One Program Fetch and Two Data Accesses for Maximum Performance
Case No.
Primary Bus
Accesses
Accesses From Dual-Access
Internal Memory
Expansion
†
Or
Peripheral Bus
Accesses
1 1 2 from any combination of internal memory —
2 1 program 1 data 1 data
3 1 data 1 data 1 program
4 1 data 1 program, 1 data 1 DMA
5—
2 from same internal memory block and 1 from
a different internal memory block
—
6 — 3 from different internal memory blocks —
7 — 2 from any combination of internal memory 1
8 1 program 2 data 1 DMA
9
1 DMA 2 data 1 program
†
The expansion bus is available only on the ’C30.