Computer Hardware User's Guide

ARs read
Resolving Register Conflicts
8-19 Pipeline Operation
8.3 Resolving Register Conflicts
If the auxiliary registers (AR7–AR0), the index registers (IR1–IR0), data-page
pointer (DP), or stack pointer (SP) are accessed for any reason other than
address generation, pipeline conflicts associated with the next memory access
can occur. The pipeline conflicts and delays are presented in Section 8.2 on
page 8-4.
Example 8–14, Example 8–15, and Example 8–16 demonstrate some common
uses of these registers that do not produce a conflict or ways that you can avoid
the conflict.
Example 8–14. Address Generation Update of an AR Followed by an AR for Address
Generation
LDF 7.0,R0 ; 7.0 → R0
MPYF *++AR0(IR1),R0
ADDF *AR2,R0
FIX
MPYF
ADDF
Pipeline Operation
PC Fetch
Decode Read Execute
n LDF — — —
n+1 MYPF LDF — —
n+2 ADDF MYPF LDF —
n+3 FIX ADDF MYPF LDF
n+4 MPYF FIX ADDF MYPF
n+5 ADDF MYPF FIX ADDF
Note: W, X, Y, Z = Instruction representations