Computer Hardware User's Guide

Fetch held
until data
access
completes
Data
accessed
Pipeline Conflicts
8-10
Example 8–5. Program Wait Until CPU Data Access Completes
ADDF3 *AR0,*AR1,R0
FIX
MPYF
ADDF3
NEGB
Pipeline Operation
PC Fetch
Decode Read Execute
n ADDF3 — — —
n+1 FIX ADDF3 — —
n+2 (wait) FIX ADDF3 —
n+2 MPYF (nop) FIX ADDF3
n+3 ADDF3 MPYF (nop) FIX
n+4 NEGB ADDF3 MPYF (nop)
Example 8–6 shows a program wait due to a multicycle data-data access or
a multicycle DMA access. The ADDF, MPYF, and SUBF are fetched from some
portion in memory other than the external port the DMA requires. The DMA
begins a multicycle access. The program fetch corresponding to the CALL is
made to the same external port that the DMA is using.
Either of two cases may produce this situation:
One of the following two memory boundaries is crossed:
From internal memory to external memory
From one external port to another
Code that has been cached is executed, and the instruction prior to the
ADDF is one of the following (conditional or unconditional):
A delayed branch instruction
A delayed decrement and branch instruction
Even though the DMA has the lowest priority on ’C30 and ’C31 or when configured
as such in the ’C32, multicycle access cannot be aborted. The program fetch must
wait until the DMA access completes.