Computer Hardware User's Guide

8-1 Pipeline Operation
Pipeline Operation
Two characteristics of the’C3x that contribute to its high performance are:
Pipelining
Concurrent I/O and CPU operation
The following four functional units control ’C3x operation:
Fetch
Decode
Read
Execute
Pipelining is the overlapping or parallel operations of the fetch, decode, read,
and execute levels of a basic instruction.
The DMA controller decreases pipeline interference and enhances the CPU’s
computational throughput by performing input/output operations.
Topic Page
8.1 Pipeline Structure 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Pipeline Conflicts 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Resolving Register Conflicts 8-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 Memory Access for Maximum Performance 8-22. . . . . . . . . . . . . . . . . . . .
8.5 Clocking Memory Accesses 8-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 8