Computer Hardware User's Guide
Reset Operation
7-23
Program Flow Control
Table 7–3. TMS320C3x Pin Operation at Reset (Continued)
Device
Signal ‘C32‘C31‘C30Operation at Reset
DR1 Asynchronous reset; placed in high-impedance state
FSR1 Asynchronous reset; placed in high-impedance state
Timer0 Signal
TCLK0 Asynchronous reset; placed in high-impedance state
Timer1 Signal
TCLK1 Asynchronous reset; placed in high-impedance state
Supply and Oscillator Signals
V
DD
Reset has no effect
IODV
DD
Reset has no effect
ADV
DD
Reset has no effect
PDV
DD
Reset has no effect
DDV
DD
Reset has no effect
MDV
DD
Reset has no effect
V
SS
Reset has no effect
DV
SS
Reset has no effect
CV
SS
Reset has no effect
IV
SS
Reset has no effect
V
BBP
Reset has no effect
V
SUBS
Reset has no effect
X1 Reset has no effect
X2/CLKIN Reset has no effect
H1 Synchronous reset; will go to its initial state when RESET
makes a 1 to 0 transition
H3
Synchronous reset; will go to its initial state when RESET
makes a 1 to 0 transition