Computer Hardware User's Guide

Reset Operation
7-22
Table 7–3. TMS320C3x Pin Operation at Reset (Continued)
Device
Signal ‘C32‘C31‘C30Operation at Reset
HOLDA Reset has no effect
PRGW Reset has no effect
Expansion Bus Interface
XD31–XD0 Synchronous reset; placed in high-impedance state
XA12–XA0 Synchronous reset; placed in high-impedance state
XR/W
Synchronous reset; placed in high-impedance state
MSTRB
Synchronous reset; deasserted by going to a high level
XRDY
Reset has no effect
Control Signals
RESET Reset input pin
INT3–INT0 Reset has no effect
IACK
Synchronous reset; deasserted by going to a high level
MC/MP
or MCBL/MP Reset has no effect
SHZ
Reset has no effect
XF1–XF0 Asynchronous reset; placed in high-impedance state
Serial Port 0 Signals
CLKX0 Asynchronous reset; placed in high-impedance state
DX0 Asynchronous reset; placed in high-impedance state
FSX0 Asynchronous reset; placed in high-impedance state
CLKR0 Asynchronous reset; placed in high-impedance state
DR0 Asynchronous reset; placed in high-impedance state
FSR0 Asynchronous reset; placed in high-impedance state
Serial Port 1 Signals
CLKX1 Asynchronous reset; placed in high-impedance state
DX1 Asynchronous reset; placed in high-impedance state
FSX1 Asynchronous reset; placed in high-impedance state
CLKR1
Asynchronous reset; placed in high-impedance state