Computer Hardware User's Guide
Figures
xxi
Contents
5–1 Short-Integer Format and Sign-Extension of Short Integers 5-2. . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Single-Precision Integer Format 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Short Unsigned-Integer Format and Zero Fill 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Single-Precision Unsigned-Integer Format 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 General Floating-Point Format 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Short Floating-Point Format 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 TMS320C32 Short Floating-Point Format for External 16-Bit Data 5-6. . . . . . . . . . . . . . . . . . .
5–8 Single-Precision Floating-Point Format 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 Extended-Precision Floating-Point Format 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10 Converting from Short Floating-Point Format to Single-Precision
Floating-Point Format 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 Converting from Short Floating-Point Format to Extended-Precision
Floating-Point Format 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–12 Converting from Single-Precision Floating-Point Format to Extended-Precision
Floating-Point Format 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–13 Converting from Extended-Precision Floating-Point Format to Single-Precision
Floating-Point Format 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–14 IEEE Single-Precision Std. 754 Floating-Point Format 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–15 TMS320C3x Single-Precision 2s-Complement Floating-Point Format 5-15. . . . . . . . . . . . . . .
5–16 Flowchart for Floating-Point Multiplication 5-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–17 Flowchart for Floating-Point Addition 5-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–18 Flowchart for NORM Instruction Operation 5-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–19 Flowchart for Floating-Point Rounding by the RND Instruction 5-40. . . . . . . . . . . . . . . . . . . . .
5–20 Flowchart for Floating-Point to Integer Conversion by FIX Instruction 5-42. . . . . . . . . . . . . . .
5–21 Flowchart for Integer to Floating-Point Conversion by FLOAT Instruction 5-43. . . . . . . . . . . .
5–22 Tabulated Values for Mantissa 5-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–23 Fast Logarithm for FFT Displays 5-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Direct Addressing 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Indirect Addressing Operand Encoding 6-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Encoding for 24-Bit PC-Relative Addressing Mode 6-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 Logical and Physical Representation of Circular Buffer 6-21. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–5 Logical and Physical Representation of Circular Buffer after Writing Three Values 6-21. . . .
6–6 Logical and Physical Representation of Circular Buffer after Writing Eight Values 6-22. . . . .
6–7 Circular Buffer Implementation 6-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–8 Data Structure for FIR Filters 6-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–9 System Stack Configuration 6-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–10 Implementations of High-to-Low Memory Stacks 6-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–11 Implementations of Low-to-High Memory Stacks 6-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 CALL Response Timing 7-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Multiple TMS320C3xs Sharing Global Memory 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 Zero-Logic Interconnect of TMS320C3x Devices 7-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–4 Effective Base Address of the Interrupt-Trap-Vector Table 7-29. . . . . . . . . . . . . . . . . . . . . . . . .
7–5 IF Register Modification 7-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–6 CPU Interrupt Processing 7-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–7 Interrupt Logic Functional Diagram 7-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .