Computer Hardware User's Guide

Indirect Addressing
6-6
Figure 6–2. Indirect Addressing Operand Encoding
LSBMSB
5 bits
mod ARn disp
3 bits 0, 5, or 8 bits
Note: Auxiliary Register
The auxiliary register (AR n ) is encoded in the instruction word according to its
binary representation n (for example, AR3 is encoded as 11
2
), not its register
machine address (shown in Table 6–1).