Calculator User Manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index

Index
Index-21
status registers ST0 and ST1
addresses and reset values A-2
bits 3-15
clear control bit (CLRC instruction) 7-62
introduction 3-15
load (LST instruction) 7-87
load data page pointer (LDP instruction) 7-83
modify auxiliary register pointer (MAR instruc-
tion) 7-111
quick reference A-5
set control bit (SETC instruction) 7-155
set product shift mode (SPM instruction) 7-167
store (SST instruction) 7-172
STB bit 10-8
STRB
(external access active strobe) 4-3
SUB instruction 7-174
SUBB instruction 7-178
SUBC instruction 7-180
SUBS instruction 7-182
SUBT instruction 7-184
subtract.
See
accumulator instructions
SXM (sign-extension mode bit)
definition 3-17
effect on CALU (central arithmetic logic
unit) 3-9
effect on input shifter 3-4
synchronous serial port
See also
synchronous serial port registers
basic operation 9-6
bit input from CLKR pin (IN0 bit) 9-10
block diagram 9-3
burst mode (introduction) 9-12
CLKR pin as bit input (IN0 bit) 9-10
clock source for transmission (MCM bit) 9-12
components 9-3
configuration 9-8
continuous mode (introduction) 9-12
controlling and resetting 9-8
digital loopback mode 9-28
emulation modes 9-8, 9-28
error conditions
burst mode 9-29
continuous mode 9-29
features 9-1
synchronous serial port
(continued)
FIFO buffers
detecting data in receive FIFO buffer (RFNE
bit) 9-9
detecting empty transmit FIFO buffer (TCOMP
bit) 9-9
introduction 9-5
managing contents with SDTR 9-15
frame sync modes (FSM bit) 9-12
frame sync source for transmission (TXM
bit) 9-13
interrupts (XINT and RINT)
flag bits 5-21
mask bits 5-23
priorities 5-16
receive (RINT) 9-6
controlling (FR1 and FR0 bits) 9-10
transmit (XINT) 9-6
controlling (FT1 and FT0 bits) 9-9
using 9-13
vector locations 5-16
introduction 2-12
overflow in receiver
burst mode 9-29
continuous mode 9-30
detecting (OVF bit) 9-10
overview 9-2
pins 9-4
receiver operation 9-24
burst mode 9-24
continuous mode 9-25
registers (overview) 9-5
reset conditions 5-34
resetting 9-13
receiver (RRST bit) 9-10
transmitter (XRST bit) 9-10
selecting mode of operation 9-12
selecting transmit clock source 9-12
selecting transmit frame sync source 9-12
signals 9-3
testing 9-27
transmitter operation 9-16
burst mode with external frame sync 9-18
burst mode with internal frame sync 9-16
continuous mode with external frame
sync 9-22
continuous mode with internal frame
sync 9-20