Calculator User Manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index

Index
Index-17
PREG instructions
(continued)
load high bits of PREG (LPH) 7-85
set PREG output shift mode (SPM) 7-167
store high word of PREG to data memory
(SPH) 7-161
store low word of PREG to data memory
(SPL) 7-163
store PREG to accumulator (PAC instruc-
tion) 7-134
store PREG to accumulator and load TREG
(LTP) 7-98
subtract PREG from accumulator (SPAC) 7-160
subtract PREG from accumulator and load TREG
(LTS) 7-100
subtract PREG from accumulator and multiply
(MPYS) 7-118
subtract PREG from accumulator and square
specified value (SQRS) 7-170
product register (PREG) 3-6
product shift mode bits (PM) 3-17
product shift modes 3-7
product shifter 3-6
program address bus (PAB)
definition 2-3
used in program-memory address genera-
tion 5-3
program address register (PAR)
definition F-16
shown in figure 5-2
program control features
See also
interrupts
address generation, program memory 5-2
branch instructions
conditional 5-11
unconditional 5-8
call instructions
conditional 5-12
unconditional 5-8
conditional instructions 5-10 to 5-13
conditions that may be tested 5-10 to 5-13
stabilization of conditions 5-11 to 5-13
using multiple conditions 5-10
pipeline operation 5-7
program counter (PC) 5-3
loading 5-4
program control features
(continued)
repeating a single instruction 5-14
reset conditions 5-33
return instructions
conditional 5-12
unconditional 5-9
stack 5-4
status registers ST0 and ST1 3-15
bits 3-15
program counter (PC) 5-3
description 5-3
loading 5-4
shown in figure 5-2
program examples C-1 to C-24
about the examples C-2
asynchronous serial port
automatic baud-rate detection test C-16
delta interrupts C-18
transmission C-13
transmission loopback test C-14
boot loader code
command file C-24
hex conversion file C-24
command file (generic) C-5
delay loops C-8
header file with I/O register declarations C-6
header file with interrupt vector declara-
tions C-7
HOLD operation C-11
interrupt INT1
C-10
interrupts INT2 and INT3 C-12
synchronous serial port
transmission (continuous mode) C-20
using with codec C-21
timer C-9
program memory
address generation logic 5-2
micro stack (MSTACK) 5-6
program counter (PC) 5-3
stack 5-4
address map
’C203 4-32
’C204 4-35
’C209 11-6
address sources 5-3