Calculator User Manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index

F-10
G
general-purpose input/output pins: Pins that can be used to accept input
signals and/or send output signals but are not linked to specific uses.
These pins are the input pin BIO
, the output pin XF, and the input/output
pins IO0, IO1, IO2, and IO3. (IO0–IO3 are not available on the ’C209.)
global data space: One of the four ’C2xx address spaces. The global data
space can be used to share data with other processors within a system
and can serve as additional data space. See also
local data space
.
GREG:
Global memory allocation register
. A memory-mapped register
used for specifying the size of the global data memory. Addresses not
allocated by the GREG for global data memory are available for local
data memory.
H
hardware interrupt: An interrupt triggered through physical connections
with on-chip peripherals or external devices.
HOLD
: An input signal that allows external devices to request control of the
external buses. If an external device drives the HOLD
/INT1 pin low and
the CPU sends an acknowledgement at the HOLDA
pin, the external de-
vice has control of the buses until it drives HOLD
high or a nonmaskable
hardware interrupt is generated. If HOLD
is not used, it should be pulled
high.
HOLDA
:
HOLD acknowledge signal
. An output signal sent to the HOLDA pin
by the CPU in acknowledgement of a properly initiated HOLD operation.
When HOLDA
is low, the processor is in a holding state and the address,
data, and memory-control lines are available to external circuitry.
HOLD operation: An operation on the ’C2xx that allows for direct memory
access of external memory and I/O devices. A HOLD operation is initi-
ated by a HOLD
/INT1 interrupt. When the corresponding interrupt ser-
vice routine executes an IDLE instruction, the external buses enter the
high-impedance state and the HOLDA
signal is asserted. The buses re-
turn to their normal state, and the HOLD operation is concluded, when
the processor exits the IDLE state.
I
IACK: See
interrupt acknowledge signal (IACK)
.
Glossary