Calculator User Manual

Troubleshooting
9-30
Overflow. Overflow occurs when the RSR has new data to pass to the
receive FIFO buffer but the FIFO buffer is full. Overflow errors are fatal to
a reception. For as long as the FIFO buffer is full, any incoming words will
be lost. To restart reception, make space in the buffer by reading from it
(through the SDTR).
Frame sync pulse during a transmission. After the initial frame sync,
no others should occur during transmission. If a frame sync pulse occurs
during a transmission, the current transmission is aborted, and a new
transmit cycle begins.
Frame sync pulse during a reception. After the initial frame sync, no
others should occur during reception. If a frame sync pulse occurs during
a reception, the current packet of data is lost. On any FSR pulse, the RSR
bit counter is reset; therefore, the data that was being shifted into the RSR
from the the DR pin is lost.