Datasheet

S
SPICTL.0
SPIINTFLAG
SPIINT
ENA
SPISTS.6
S
Clock
Polarity
Talk
LSPCLK
456 123 0
0123
SPIBitRate
StateControl
SPIRXBUF
BufferRegister
Clock
Phase
Receiver
OverrunFlag
SPICTL.4
Overrun
INTENA
SPICCR.3 − 0
SPIBRR.6 − 0
SPICCR.6 SPICTL.3
SPIDAT.15 − 0
SPICTL.1
M
S
M
Master/Slave
SPISTS.7
SPIDAT
DataRegister
M
S
SPICTL.2
SPIChar
SPISIMO
SPISOMI
SPICLK
SW2
S
M
M
S
SW3
ToCPU
M
SW1
SPITXBUF
BufferRegister
RXFIFO_0
RXFIFO_1
−−−−−
RXFIFO_15
TXFIFOregisters
TXFIFO_0
TXFIFO_1
−−−−−
TXFIFO_15
RXFIFOregisters
16
16
16
TXInterrupt
Logic
RXInterrupt
Logic
SPIINT/SPIRXINT
SPITXINT
SPIFFOVFFLAG
SPIFFRX.15
16
TXFIFOInterrupt
RXFIFOInterrupt
SPIRXBUF
SPITXBUF
SPIFFTX.14
SPIFFENA
SPISTE
(A)
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012 www.ti.com
Figure 4-14 is a block diagram of the SPI in slave mode.
A. SPISTE is driven low by the master for a slave device.
Figure 4-14. SPI Module Block Diagram (Slave Mode)
90 Peripherals Copyright © 2009–2012, Texas Instruments Incorporated
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TMS320C28341