Datasheet

TMS320C28346, TMS320C28345, TMS320C28344

TMS320C28343, TMS320C28342, TMS320C28341

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SPRS516D –MARCH 2009–REVISED AUGUST 2012

Enhanced features:

• 16-level transmit/receive FIFO

• Delayed transmit control

The SPI port operation is configured and controlled by the registers listed in Table 4-13 and Table 4-14 .

Table 4-13. SPI-A Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

(1)

SPICCR 0x7040 1 SPI-A Configuration Control Register

SPICTL 0x7041 1 SPI-A Operation Control Register

SPISTS 0x7042 1 SPI-A Status Register

SPIBRR 0x7044 1 SPI-A Baud Rate Register

SPIRXEMU 0x7046 1 SPI-A Receive Emulation Buffer Register

SPIRXBUF 0x7047 1 SPI-A Serial Input Buffer Register

SPITXBUF 0x7048 1 SPI-A Serial Output Buffer Register

SPIDAT 0x7049 1 SPI-A Serial Data Register

SPIFFTX 0x704A 1 SPI-A FIFO Transmit Register

SPIFFRX 0x704B 1 SPI-A FIFO Receive Register

SPIFFCT 0x704C 1 SPI-A FIFO Control Register

SPIPRI 0x704F 1 SPI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

Table 4-14. SPI-D Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

(1)

SPICCR 0x7780 1 SPI-D Configuration Control Register

SPICTL 0x7781 1 SPI-D Operation Control Register

SPISTS 0x7782 1 SPI-D Status Register

SPIBRR 0x7784 1 SPI-D Baud Rate Register

SPIRXEMU 0x7786 1 SPI-D Receive Emulation Buffer Register

SPIRXBUF 0x7787 1 SPI-D Serial Input Buffer Register

SPITXBUF 0x7788 1 SPI-D Serial Output Buffer Register

SPIDAT 0x7789 1 SPI-D Serial Data Register

SPIFFTX 0x778A 1 SPI-D FIFO Transmit Register

SPIFFRX 0x778B 1 SPI-D FIFO Receive Register

SPIFFCT 0x778C 1 SPI-D FIFO Control Register

SPIPRI 0x778F 1 SPI-D Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

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