Datasheet

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012 www.ti.com
Table 4-12. SCI-C Registers
(1) (2)
NAME ADDRESS SIZE (x16) DESCRIPTION
SCICCRC 0x7770 1 SCI-C Communications Control Register
SCICTL1C 0x7771 1 SCI-C Control Register 1
SCIHBAUDC 0x7772 1 SCI-C Baud Register, High Bits
SCILBAUDC 0x7773 1 SCI-C Baud Register, Low Bits
SCICTL2C 0x7774 1 SCI-C Control Register 2
SCIRXSTC 0x7775 1 SCI-C Receive Status Register
SCIRXEMUC 0x7776 1 SCI-C Receive Emulation Data Buffer Register
SCIRXBUFC 0x7777 1 SCI-C Receive Data Buffer Register
SCITXBUFC 0x7779 1 SCI-C Transmit Data Buffer Register
SCIFFTXC
(2)
0x777A 1 SCI-C FIFO Transmit Register
SCIFFRXC
(2)
0x777B 1 SCI-C FIFO Receive Register
SCIFFCTC
(2)
0x777C 1 SCI-C FIFO Control Register
SCIPRC 0x777F 1 SCI-C Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
86 Peripherals Copyright © 2009–2012, Texas Instruments Incorporated
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