Datasheet

( )

CLKSRG

CLKG =

1 + CLKGDV

TMS320C28346, TMS320C28345, TMS320C28344

TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516D –MARCH 2009–REVISED AUGUST 2012

4.8 Multichannel Buffered Serial Port (McBSP) Module

The McBSP module has the following features:

• Compatible to McBSP in TMS320C54x™/ TMS320C55x™ DSP devices

• Full-duplex communication

• Double-buffered data registers that allow a continuous data stream

• Independent framing and clocking for receive and transmit

• External shift clock generation or an internal programmable frequency shift clock

• A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits

• 8-bit data transfers with LSB or MSB first

• Programmable polarity for both frame synchronization and data clocks

• Highly programmable internal clock and frame generation

• Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially

connected A/D and D/A devices

• Works with SPI-compatible devices

• The following application interfaces can be supported on the McBSP:

– T1/E1 framers

– IOM-2 compliant devices

– AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)

– IIS-compliant devices

– SPI

• McBSP clock rate,

where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O

buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less

than the I/O buffer speed limit.

NOTE

See Section 6 for maximum I/O pin toggling speed.

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TMS320C28341