Datasheet

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
List of Tables
2-1 C2834x Hardware Features .................................................................................................... 13
2-2 Signal Descriptions............................................................................................................... 23
3-1 Wait-states ........................................................................................................................ 39
3-2 Boot Mode Selection............................................................................................................. 42
3-3 Peripheral Frame 0 Registers .................................................................................................. 46
3-4 Peripheral Frame 1 Registers .................................................................................................. 46
3-5 Peripheral Frame 2 Registers .................................................................................................. 47
3-6 Peripheral Frame 3 Registers .................................................................................................. 47
3-7 Device Emulation Registers..................................................................................................... 47
3-8 PIE Peripheral Interrupts ....................................................................................................... 50
3-9 PIE Configuration and Control Registers...................................................................................... 51
3-10 External Interrupt Registers..................................................................................................... 52
3-11 PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 54
3-12 PLL Settings ...................................................................................................................... 57
3-13 CLKIN Divide Options ........................................................................................................... 57
3-14 Possible PLL Configuration Modes ............................................................................................ 58
3-15 Low-Power Modes ............................................................................................................... 60
4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 64
4-2 ePWM1-4 Control and Status Registers ...................................................................................... 66
4-3 ePWM5-9 Control and Status Registers ...................................................................................... 67
4-4 eCAP Control and Status Registers ........................................................................................... 71
4-5 eQEP Control and Status Registers ........................................................................................... 73
4-6 External ADC Interface Registers ............................................................................................. 74
4-7 McBSP Register Summary...................................................................................................... 77
4-8 3.3-V eCAN Transceivers ...................................................................................................... 80
4-9 CAN Register Map .............................................................................................................. 83
4-10 SCI-A Registers .................................................................................................................. 85
4-11 SCI-B Registers .................................................................................................................. 85
4-12 SCI-C Registers ................................................................................................................. 86
4-13 SPI-A Registers................................................................................................................... 89
4-14 SPI-D Registers .................................................................................................................. 89
4-15 I2C-A Registers................................................................................................................... 92
4-16 GPIO Registers .................................................................................................................. 94
4-17 GPIO-A Mux Peripheral Selection Matrix .................................................................................... 95
4-18 GPIO-B Mux Peripheral Selection Matrix .................................................................................... 96
4-19 GPIO-C Mux Peripheral Selection Matrix .................................................................................... 97
4-20 XINTF Configuration and Control Register Mapping....................................................................... 100
5-1 TMS320x2834x Delfino Peripheral Selection Guide ....................................................................... 103
6-1 TMS320C28346/C28344 Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT................. 109
6-2 TMS320C28345/C28343 Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT................. 110
6-3 Typical Current Consumption by Various Peripherals .................................................................... 112
6-4 Clocking and Nomenclature (300-MHz Devices) ........................................................................... 115
6-5 Clocking and Nomenclature (200-MHz Devices) ........................................................................... 116
6-6 XCLKIN/X1 Timing Requirements – PLL Enabled ......................................................................... 117
6-7 XCLKIN/X1 Timing Requirements – PLL Disabled ........................................................................ 117
6-8 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 117
6-9 Power Management and Supervisory Circuit Solutions ................................................................... 119
Copyright © 2009–2012, Texas Instruments Incorporated List of Tables 7