Datasheet

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
List of Figures
2-1 C2834x 179-Ball ZHH MicroStar BGA™ Upper Left Quadrant (Bottom VIew) .......................................... 16
2-2 C2834x 179-Ball ZHH MicroStar BGA™ Upper Right Quadrant (Bottom View)......................................... 17
2-3 C2834x 179-Ball ZHH MicroStar BGA™ Lower Left Quadrant (Bottom View)........................................... 18
2-4 C2834x 179-Ball ZHH MicroStar BGA™ Lower Right Quadrant (Bottom View)......................................... 19
2-5 C2834x 256-Ball ZFE Plastic BGA Upper Left Quadrant (Bottom View) ................................................. 20
2-6 C2834x 256-Ball ZFE Plastic BGA Upper Right Quadrant (Bottom View) ............................................... 21
2-7 C2834x 256-Ball ZFE Plastic BGA Lower Left Quadrant (Bottom View) ................................................. 22
2-8 C2834x 256-Ball ZFE Plastic BGA Lower Right Quadrant (Bottom View) ............................................... 22
3-1 Functional Block Diagram ...................................................................................................... 35
3-2 C28346, C28345 Memory Map ................................................................................................ 37
3-3 C28344, C28343 Memory Map ................................................................................................ 38
3-4 C28342, C28341 Memory Map ................................................................................................ 39
3-5 External and PIE Interrupt Sources............................................................................................ 49
3-6 External Interrupts................................................................................................................ 49
3-7 Multiplexing of Interrupts Using the PIE Block ............................................................................... 50
3-8 Clock and Reset Domains ...................................................................................................... 53
3-9 OSC and PLL Block Diagram................................................................................................... 54
3-10 Using a 3.3-V External Oscillator............................................................................................... 55
3-11 Using a 1.8-V External Oscillator............................................................................................... 55
3-12 Using the Internal Oscillator .................................................................................................... 55
3-13 Watchdog Module ................................................................................................................ 59
4-1 DMA Functional Block Diagram ................................................................................................ 62
4-2 CPU-Timers....................................................................................................................... 63
4-3 CPU-Timer Interrupt Signals and Output Signal ............................................................................. 63
4-4 Generation of SOC Pulses to the External ADC Module ................................................................... 65
4-5 ePWM Submodules Showing Critical Internal Signal Interconnections ................................................... 68
4-6 eCAP Functional Block Diagram ............................................................................................... 70
4-7 eQEP Functional Block Diagram............................................................................................... 72
4-8 External ADC Interface .......................................................................................................... 74
4-9 McBSP Module .................................................................................................................. 76
4-10 eCAN Block Diagram and Interface Circuit ................................................................................... 79
4-11 eCAN-A Memory Map ........................................................................................................... 81
4-12 eCAN-B Memory Map ........................................................................................................... 82
4-13 Serial Communications Interface (SCI) Module Block Diagram............................................................ 87
4-14 SPI Module Block Diagram (Slave Mode) .................................................................................... 90
4-15 I2C Peripheral Module Interfaces .............................................................................................. 91
4-16 GPIO MUX Block Diagram...................................................................................................... 93
4-17 Qualification Using Sampling Window......................................................................................... 98
4-18 External Interface Block Diagram .............................................................................................. 99
4-19 Typical 16-bit Data Bus XINTF Connections................................................................................ 100
4-20 Typical 32-bit Data Bus XINTF Connections................................................................................ 100
5-1 Example of C2834x Device Nomenclature .................................................................................. 102
6-1 Temperature Versus Leakage Current (Typical)............................................................................ 111
6-2 Emulator Connection Without Signal Buffering for the MCU ............................................................. 113
6-3 3.3-V Test Load Circuit......................................................................................................... 114
6-4 Clock Timing..................................................................................................................... 117
6-5 Power-on Reset................................................................................................................. 120
Copyright © 2009–2012, Texas Instruments Incorporated List of Figures 5