Datasheet

WDINT
LPMINT
Watchdog
LowPowerModels
Sync
SYSCLKOUT
WAKEINT
DMA
Clear
Peripherals
(SPI,SCI,I2C,CAN,McBSP
)
(A),
EPWM,ECAP,EQEP
DMA
XINT1
InterruptControl
XINT1CR(15:0)
XINT1CTR(15:0)
XINT1
Latch
MUX
GPIOXINT1SEL(4:0)
DMA
XINT2
InterruptControl
XINT2CR(15:0)
XINT2CTR(15:0)
XINT2
Latch
MUX
GPIOXINT2SEL(4:0)
DMA
TINT0
CPUTimer0
DMA
TINT2
CPUTimer2
CPUTimer1
MUX
TINT1
InterruptControl
XNMICR(15:0)
XNMICTR(15:0)
MUX
1
DMA
NMI
INT13
INT14
INT1
to
INT12
C28
Core
96Interrupts
PIE
XNMI_
XINT13
Latch
MUX
GPIOXNMISEL(4:0)
GPIO
Mux
GPIO0.int
GPIO31.int
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012 www.ti.com
3.5 Interrupts
Figure 3-5 shows how the various interrupt sources are multiplexed.
A. DMA-accessible
Figure 3-5. External and PIE Interrupt Sources
48 Functional Overview Copyright © 2009–2012, Texas Instruments Incorporated
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TMS320C28341