Datasheet
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012
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Table 2-2. Signal Descriptions (continued)
ZHH ZFE
NAME DESCRIPTION
BALL # BALL #
Reset
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the MCU when a watchdog reset occurs.
XRS P8 T10
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin
be driven by an open-drain device.
XRS I/O Control (I) - This pin must be connected to the XRS pin on the target board. When XRS is
XRSIO N8 T9 low (reset), the level detected on this pin puts all output buffers on the device in high-impedance
mode.
External ADC Interface Signals
EXTSOC1A N1 M2 External ADC SOC Group 1 A Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCA internal signals (O)
EXTSOC1B M3 M3 External ADC SOC Group 1 B Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCB internal signals (O)
EXTSOC2A M2 N1 External ADC SOC Group 2 A Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCA internal signals (O)
EXTSOC2B P1 N2 External ADC SOC Group 2 B Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCB internal signals (O)
EXTSOC3A N2 N3 External ADC SOC Group 3 A Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCA internal signals (O)
EXTSOC3B P2 P2 External ADC SOC Group3 B Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCB internal signals (O)
EXTADCCLK N3 R3 External ADC Clock Signal. Clock for external ADC support, derived from SYSCLK (O)
GPIO and Peripheral Signals
GPIO0 General purpose input/output 0 (I/O/Z)
EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)
B1 D2
- -
- -
GPIO1 General purpose input/output 1 (I/O/Z)
EPWM1B Enhanced PWM1 Output B (O)
C1 E1
ECAP6 Enhanced Capture 6 input/output (I/O)
MFSRB McBSP-B receive frame synch (I/O)
GPIO2 General purpose input/output 2 (I/O/Z)
EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)
F5 E2
- -
- -
GPIO3 General purpose input/output 3 (I/O/Z)
EPWM2B Enhanced PWM2 Output B (O)
E4 E3
ECAP5 Enhanced Capture 5 input/output (I/O)
MCLKRB McBSP-B receive clock (I/O)
GPIO4 General purpose input/output 4 (I/O/Z)
EPWM3A Enhanced PWM3 output A and HRPWM channel (O)
E2 F1
- -
- -
GPIO5 General purpose input/output 5 (I/O/Z)
EPWM3B Enhanced PWM3 output B (O)
E3 F2
MFSRA McBSP-A receive frame synch (I/O)
ECAP1 Enhanced Capture input/output 1 (I/O)
GPIO6 General purpose input/output 6 (I/O/Z)
EPWM4A Enhanced PWM4 output A and HRPWM channel (O)
F3 F3
EPWMSYNCI External ePWM sync pulse input (I)
EPWMSYNCO External ePWM sync pulse output (O)
GPIO7 General purpose input/output 7 (I/O/Z)
EPWM4B Enhanced PWM4 output B (O)
F2 G1
MCLKRA McBSP-A receive clock (I/O)
ECAP2 Enhanced capture input/output 2 (I/O)
24 Introduction Copyright © 2009–2012, Texas Instruments Incorporated
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