Datasheet

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
Contents
1 TMS320C2834x ( Delfino™) MCUs ....................................................................................... 10
1.1 Overview .................................................................................................................... 10
1.2 Features .................................................................................................................... 10
1.3 Getting Started ............................................................................................................. 11
2 Introduction ...................................................................................................................... 12
2.1 Pin Assignments ........................................................................................................... 15
2.2 Signal Descriptions ........................................................................................................ 23
3 Functional Overview .......................................................................................................... 34
3.1 Memory Maps .............................................................................................................. 35
3.2 Brief Descriptions .......................................................................................................... 40
3.2.1 C28x CPU ....................................................................................................... 40
3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 40
3.2.3 Peripheral Bus .................................................................................................. 40
3.2.4 Real-Time JTAG and Analysis ................................................................................ 41
3.2.5 External Interface (XINTF) .................................................................................... 41
3.2.6 M0, M1 SARAMs ............................................................................................... 41
3.2.7 L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs ....................................... 41
3.2.8 Boot ROM ....................................................................................................... 42
3.2.9 Security .......................................................................................................... 42
3.2.10 Peripheral Interrupt Expansion (PIE) Block ................................................................. 43
3.2.11 External Interrupts (XINT1–XINT7, XNMI) .................................................................. 43
3.2.12 Oscillator and PLL .............................................................................................. 43
3.2.13 Watchdog ........................................................................................................ 43
3.2.14 Peripheral Clocking ............................................................................................. 43
3.2.15 Low-Power Modes .............................................................................................. 43
3.2.16 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 44
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 44
3.2.18 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 44
3.2.19 Control Peripherals ............................................................................................. 45
3.2.20 Serial Port Peripherals ......................................................................................... 45
3.3 Register Map ............................................................................................................... 46
3.4 Device Emulation Registers .............................................................................................. 47
3.5 Interrupts .................................................................................................................... 48
3.5.1 External Interrupts .............................................................................................. 52
3.6 System Control ............................................................................................................ 53
3.6.1 OSC and PLL Block ............................................................................................ 54
3.6.1.1 External Reference Oscillator Clock Option .................................................... 56
3.6.1.2 PLL-Based Clock Module ......................................................................... 57
3.6.1.3 Loss of Input Clock ................................................................................ 58
3.6.2 Watchdog Block ................................................................................................. 59
3.7 Low-Power Modes Block ................................................................................................. 60
4 Peripherals ....................................................................................................................... 61
4.1 DMA Overview ............................................................................................................. 61
4.2 32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2 ..................................................................... 63
4.3 Enhanced PWM Modules ................................................................................................ 65
4.4 High-Resolution PWM (HRPWM) ....................................................................................... 69
4.5 Enhanced CAP Modules ................................................................................................. 70
4.6 Enhanced QEP Modules ................................................................................................. 72
4.7 External ADC Interface ................................................................................................... 73
4.8 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 75
4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) .................................... 78
2 Contents Copyright © 2009–2012, Texas Instruments Incorporated