Datasheet

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M35
M37
M40
M39
M38
M34
LSB
MSB
M41
M42
M36
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
Table 6-52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M39 t
su(DRV-CKXH)
Setup time, DR valid before CLKX high 30 8P – 10 ns
M40 t
h(CKXH-DRV)
Hold time, DR valid after CLKX high 1 8P – 10 ns
M41 t
su(FXL-CKXH)
Setup time, FSX low before CLKX high 16P + 10 ns
M42 t
c(CKX)
Cycle time, CLKX 2P
(1)
16P ns
(1) 2P = 1/CLKG
Table 6-53. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
MASTER SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M34 t
h(CKXL-FXL)
Hold time, FSX low after CLKX low P ns
M35 t
d(FXL-CKXH)
Delay time, FSX low to CLKX high 2P
(1)
ns
M36 t
d(CLKXL-DXV)
Delay time, CLKX low to DX valid –2 0 3P + 6 5P + 20 ns
M37 t
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit P + 6 7P + 6 ns
from CLKX low
M38 t
d(FXL-DXV)
Delay time, FSX low to DX valid 6 4P + 6 ns
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With a maximum LSPCLK speed of 150 MHz, CLKX maximum
frequency is LSPCLK/16; that is, 9.375 MHz and P = 6.67 ns.
Figure 6-32. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
Copyright © 2009–2012, Texas Instruments Incorporated Electrical Specifications 161
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