Datasheet

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012 www.ti.com
Table 6-49. McBSP Switching Characteristics
(1) (2)
NO. PARAMETER MIN MAX UNIT
M1 t
c(CKRX)
Cycle time, CLKR/X CLKR/X int 2P ns
M2 t
w(CKRXH)
Pulse duration, CLKR/X high CLKR/X int D – 2
(3)
D + 2
(3)
ns
M3 t
w(CKRXL)
Pulse duration, CLKR/X low CLKR/X int C – 2
(3)
C + 2
(3)
ns
M4 t
d(CKRH-FRV)
Delay time, CLKR high to internal FSR valid CLKR int 0 4 ns
CLKR ext 3 20
M5 t
d(CKXH-FXV)
Delay time, CLKX high to internal FSX valid CLKX int 0 4 ns
CLKX ext 3 20
M6 t
dis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance CLKX int 8 ns
following last data bit
CLKX ext 14
M7 t
d(CKXH-DXV)
Delay time, CLKX high to DX valid. CLKX int 4 ns
This applies to all bits except the first bit transmitted. CLKX ext 20
Delay time, CLKX high to DX valid DXENA = 0 CLKX int 4
CLKX ext 20
Only applies to first bit transmitted when DXENA = 1 CLKX int P + 4
in Data Delay 1 or 2 (XDATDLY=01b or
CLKX ext P + 20
10b) modes
M8 t
en(CKXH-DX)
Enable time, CLKX high to DX driven DXENA = 0 CLKX int 0 ns
CLKX ext 10
Only applies to first bit transmitted when DXENA = 1 CLKX int P
in Data Delay 1 or 2 (XDATDLY=01b or
CLKX ext P + 10
10b) modes
M9 t
d(FXH-DXV)
Delay time, FSX high to DX valid DXENA = 0 FSX int 4 ns
FSX ext 16
Only applies to first bit transmitted when DXENA = 1 FSX int P + 4
in Data Delay 0 (XDATDLY=00b) mode.
FSX ext P + 16
M10 t
en(FXH-DX)
Enable time, FSX high to DX driven DXENA = 0 FSX int 0 ns
FSX ext 6
Only applies to first bit transmitted when DXENA = 1 FSX int P
in Data Delay 0 (XDATDLY=00b) mode
FSX ext P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
158 Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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