Datasheet

CLKSRG
(1 ) CLKGDV)
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG can be LSPCLK, CLKX,
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
6.16 Multichannel Buffered Serial Port (McBSP) Timing
6.16.1 McBSP Transmit and Receive Timing
Table 6-48. McBSP Timing Requirements
(1) (2)
NO. MIN MAX UNIT
McBSP module clock (CLKG, CLKX, CLKR) range 1 kHz
40
(3)
MHz
McBSP module cycle time (CLKG, CLKX, CLKR) range 25 ns
1 ms
M11 t
c(CKRX)
Cycle time, CLKR/X CLKR/X ext 2P ns
M12 t
w(CKRX)
Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 4 ns
M13 t
r(CKRX)
Rise time, CLKR/X CLKR/X ext 4 ns
M14 t
f(CKRX)
Fall time, CLKR/X CLKR/X ext 4 ns
M15 t
su(FRH-CKRL)
Setup time, external FSR high before CLKR low CLKR int 20 ns
CLKR ext 2
M16 t
h(CKRL-FRH)
Hold time, external FSR high after CLKR low CLKR int 0 ns
CLKR ext 6
M17 t
su(DRV-CKRL)
Setup time, DR valid before CLKR low CLKR int 20 ns
CLKR ext 2
M18 t
h(CKRL-DRV)
Hold time, DR valid after CLKR low CLKR int 0 ns
CLKR ext 6
M19 t
su(FXH-CKXL)
Setup time, external FSX high before CLKX low CLKX int 20 ns
CLKX ext 2
M20 t
h(CKXL-FXH)
Hold time, external FSX high after CLKX low CLKX int 0 ns
CLKX ext 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (40 MHz).
Copyright © 2009–2012, Texas Instruments Incorporated Electrical Specifications 157
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