Datasheet
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
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SPRS516D –MARCH 2009–REVISED AUGUST 2012
6.15.9 XHOLD and XHOLDA Timing
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the
bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active
low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still
execute code from internal memory. If an access is made to the external interface, the CPU is stalled until
the XHOLD signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[19:0] XZCS0
XD[31:0], XD[15:0] XZCS6
XWE0, XWE1, XZCS7
XRD
XR/W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events.
Table 6-47. XHOLD/XHOLDA Timing Requirements
(1) (2) (3)
MIN MAX UNIT
t
d(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all address, data, and control 4t
c(XTIM)
+ t
c(XCO)
+ 20 ns
t
d(HL-HAL)
Delay time, XHOLD low to XHOLDA low 4t
c(XTIM)
+ 2t
c(XCO)
+ 20 ns
t
d(HH-HAH)
Delay time, XHOLD high to XHOLDA high 4t
c(XTIM)
+ 20 ns
t
d(HH-BV)
Delay time, XHOLD high to bus valid 6t
c(XTIM)
+ 20 ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT.
Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value
specified.
Copyright © 2009–2012, Texas Instruments Incorporated Electrical Specifications 155
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