Datasheet

Lead1
Active
Trail
XCLKOUT=XTIMCLK
(D)
XA[0:19]
t
d(XCOHL-XWEH)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
WS(Async)
XZCS0XZCS6XZCS7, ,
XRD
XWE0,XWE1
(E)
XR/W
t
d(XCOH-XZCSL)
t
d(XCOH-XRNWL)
t
d(XCOHL-XRNWH)
t
en(XD)XWEL
t
h(XD)XWEH
t
h(XRDYasynchL)
DOUT
t
dis(XD)XRNW
t
h(XRDYasynchH)XZCSH
(G)
(F)
=Don’tcare.Signalcanbehighorlowduringthistime.
Legend:
t
su(XRDYasynchL)XCOHL
t
su(XRDYasynchH)XCOHL
t
d(XWEL-XD
)
t
d(XCOHL-XWEL)
(A)(B)
(C)
XREADY(Asynch)
XD[31:0],XD[15:0]
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012 www.ti.com
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode only.
F. For each sample, set up time from the beginning of the access can be calculated as: E = (XWRLEAD + XWRACTIVE
-3 + n) t
c(XTIM)
– t
su(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
G. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE – 2) t
c(XTIM)
Figure 6-27. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE
N/A
(1)
N/A
(1)
N/A
(1)
1 0 ≥ 3 3 ≥ 3 1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
154 Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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TMS320C28341