Datasheet

Lead1
Active
Trail
XCLKOUT=XTIMCLK
(D)
XA[0:18]
XREADY (Synch)
XD[0:15]
XR/W
XWE
XRD
XZCS0XZCS6XZCS7, ,
t
d(XCOHL-XWEL)
t
d(XCOHL-XWEH)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
WS(Synch)
t
d(XCOH-XZCSL)
t
d(XCOH-XRNWL)
t
d(XCOHL-XRNWH)
t
en(XD)XWEL
t
h(XD)XWEH
t
su(XRDHsynchH)XCOHL
t
su(XRDYsynchL)XCOHL
DOUT
t
d(XWEL-XD
)
t
dis(XD)XRNW
t
h(XRDYsynchL)
t
h(XRDYsynchH)XZCSH
=Don’tcare.Signalcanbehighorlowduringthistime.
Legend:
(F)
(E)
(A)(B)
(C)
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode only.
F. For each sample, setup time from the beginning of the access can be calculated as E = (XWRLEAD + XWRACTIVE +
n –1) t
c(XTIM)
– t
su(XRDYsynchL)XCOH
where n is the sample number: n = 1, 2, 3, and so forth.
G. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE) t
c(XTIM)
Figure 6-26. Write With Synchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE
N/A
(1)
N/A
(1)
N/A
(1)
1 0 ≥ 3 1 ≥3 0 = XREADY
(Synch)
(1) N/A = "Don't care" for this example.
Copyright © 2009–2012, Texas Instruments Incorporated Electrical Specifications 153
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