Datasheet

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
6.15.7 External Interface Ready-on-Read Timing With One External Wait State
Table 6-40. External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER MIN MAX UNIT
t
d(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low 0 2 ns
t
d(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high –0.2 0.9 ns
t
d(XCOH-XA)
Delay time, XCLKOUT high to address valid 1.5 ns
t
d(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low –0.2 0.8 ns
t
d(XCOHL-XRDH)
Delay time, XCLKOUT high/low to XRD inactive high –0.4 0.8 ns
t
h(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(1)
ns
t
h(XA)XRD
Hold time, address valid after XRD inactive high
(1)
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Table 6-41. External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN MAX UNIT
t
a(A)
Access time, read data from address valid (LR + AR) – 13.5
(1)
ns
t
a(XRD)
Access time, read data valid from XRD active low AR – 13
(1)
ns
t
su(XD)XRD
Setup time, read data valid before XRD strobe inactive high 13 ns
t
h(XD)XRD
Hold time, read data valid after XRD inactive high 0 ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-35.
Table 6-42. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
(1)
MIN MAX UNIT
t
su(XRDYsynchL)XCOHL
Setup time, XREADY (synchronous) low before XCLKOUT high/low 8 ns
t
h(XRDYsynchL)
Hold time, XREADY (synchronous) low 1t
c(XTIM)
ns
t
su(XRDYsynchH)XCOHL
Setup time, XREADY (synchronous) high before XCLKOUT high/low 8 ns
t
h(XRDYsynchH)XZCSH
Hold time, XREADY (synchronous) held high after zone chip select high 0 ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-24:
E = (XRDLEAD + XRDACTIVE) t
c(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will finish. If XREADY (synchronous) is found to be
low, it is sampled again each t
c(XTIM)
until it is found to be high.
For each sample (n) the setup time (F) with respect to the beginning of the access can be calculated as:
F = (XRDLEAD + XRDACTIVE +n − 1) t
c(XTIM)
− t
su(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-43. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN MAX UNIT
t
su(XRDYAsynchL)XCOHL
Setup time, XREADY (asynchronous) low before XCLKOUT high/low 8 ns
t
h(XRDYAsynchL)
Hold time, XREADY (asynchronous) low 1t
c(XTIM)
ns
t
su(XRDYAsynchH)XCOHL
Setup time, XREADY (asynchronous) high before XCLKOUT high/low 8 ns
t
h(XRDYasynchH)XZCSH
Hold time, XREADY (asynchronous) held high after zone chip select high 0 ns
Copyright © 2009–2012, Texas Instruments Incorporated Electrical Specifications 149
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