Datasheet

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
6.15.6 External Interface Write Timing
Table 6-39. External Interface Write Switching Characteristics
PARAMETER MIN MAX UNIT
t
d(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low 0 2 ns
t
d(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high –0.2 0.9 ns
t
d(XCOH-XA)
Delay time, XCLKOUT high to address valid 1.5 ns
t
d(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE0, XWE1 low –0.3 0.7 ns
t
d(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE0, XWE1 high –0.5 0.5 ns
t
d(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low –0.2 1.5 ns
t
d(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high 0.3 0.6 ns
t
en(XD)XWEL
Enable time, data bus driven from XWE0, XWE1 low –7.5 ns
t
d(XWEL-XD)
Delay time, data valid after XWE0, XWE1 active low 0 4 ns
t
h(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(1)
ns
t
h(XD)XWE
Hold time, write data valid after XWE0, XWE1 inactive high TW – 7.5
(2)
ns
t
dis(XD)XRNW
Maximum time for processor to release the data bus after XR/W inactive high 0 ns
(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high.
This includes alignment cycles.
(2) TW = Trail period, write access. See Table 6-35.
Copyright © 2009–2012, Texas Instruments Incorporated Electrical Specifications 147
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