Datasheet
DIN
t
d(XCOHL-XRDL)
t
d(XCOH-XA)
t
d(XCOH-XZCSL)
t
d(XCOHL-XRDH)
t
h(XD)XRD
t
d(XCOHL-XZCSH)
XZCS0XZCS6XZCS7, ,
XA[0:19]
XRD
,XWEXWE1
(E)
XR/W
XD[0:31],XD[0:15]
t
su(XD)XRD
t
a(A)
t
a(XRD)
XREADY
(F)
Lead
Active
Trail
X OUT=XTIMCLK
(D)
CLK
(A)(B)
(C)
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012
www.ti.com
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which
remains high.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode.
F. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-22. Example Read Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE
≥ 2 ≥ 5 ≥ 0 0 0 N/A
(1)
N/A
(1)
N/A
(1)
N/A
(1)
(1) N/A = Not applicable (or “Don’t care”) for this example
146 Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,
TMS320C28341