Datasheet

1
0
/2
SYSCLKOUT
C28x
CPU
XINTCNF2(XTIMCLK)
1
0
/2
XTIMCLK
XINTCNF2
(CLKMODE)
0
1
0
XTIMING0
XTIMING6
XTIMING7
XBANK
LEAD/ACTIVE/TRAIL
PCLKR3[XINTFENCLK]
XINTCNF2
(CLKOFF)
XCLKOUT
1
0
/2
XINTCNF2
(BY4CLKMODE)
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-36.
Table 6-36. XINTF Clock Configurations for SYSCLKOUT = 300 MHz
MODE SYSCLKOUT XTIMCLK XCLKOUT
(1)
1 SYSCLKOUT SYSCLKOUT
Example: 300 MHz 300 MHz 300 MHz
2 SYSCLKOUT 1/2 SYSCLKOUT
Example: 300 MHz 300 MHz 150 MHz
3 SYSCLKOUT 1/2 SYSCLKOUT
Example: 300 MHz 300 MHz 150 MHz
4 SYSCLKOUT 1/4 SYSCLKOUT
Example: 300 MHz 300 MHz 75 MHz
5 1/2 SYSCLKOUT 1/2 SYSCLKOUT
Example: 300 MHz 150 MHz 150 MHz
6 1/2 SYSCLKOUT 1/4 SYSCLKOUT
Example: 300 MHz 150 MHz 75 MHz
7 1/2 SYSCLKOUT 1/4 SYSCLKOUT
Example: 300 MHz 150 MHz 75 MHz
8 1/2 SYSCLKOUT 1/8 SYSCLKOUT
Example: 300 MHz 150 MHz 37.5 MHz
(1) The XCLKOUT signal is limited to a maximum frequency of 75 MHz.
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6-21.
Figure 6-21. Relationship Between XTIMCLK and SYSCLKOUT
Copyright © 2009–2012, Texas Instruments Incorporated Electrical Specifications 143
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