Datasheet

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
6.15.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
1 Lead: LR ≥ 2 × t
c(XTIM)
LW ≥ 3 × t
c(XTIM)
2 Active: AR ≥ 6 × t
c(XTIM)
AW ≥ 2 × t
c(XTIM)
3 Trail: TW ≥ 3 × t
c(XTIM)
NOTE
Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions (based on 300-MHz
system clock speed):
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
≥ 2 ≥ 5 ≥ 0 ≥ 3
(1)
≥ 1 ≥ 3
(1)
0
(2)
(1) Lead and trail write must be at least 7.5 ns.
(2) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
Examples of valid and invalid timing when using synchronous XREADY:
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
Invalid
(1)
0 0 0 0 0 0 0, 1
Invalid
(1)
1 0 0 1 0 0 0, 1
Valid
(2)
2 5 0 3 1 3 0
(3)
(1) No hardware to detect illegal XTIMING configurations
(2) Based on 300-MHz system clock speed
(3) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
Copyright © 2009–2012, Texas Instruments Incorporated Electrical Specifications 141
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