Datasheet

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012 www.ti.com
6.15 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone. Table 6-35 shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 6-35. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DURATION (ns)
(1) (2)
DESCRIPTION
X2TIMING = 0 X2TIMING = 1
LR Lead period, read access XRDLEAD × t
c(XTIM)
(XRDLEAD × 2) × t
c(XTIM)
AR Active period, read access (XRDACTIVE + WS + 1) × t
c(XTIM)
(XRDACTIVE × 2 + WS + 1) × t
c(XTIM)
TR Trail period, read access XRDTRAIL × t
c(XTIM)
(XRDTRAIL × 2) × t
c(XTIM)
LW Lead period, write access XWRLEAD × t
c(XTIM)
(XWRLEAD × 2) × t
c(XTIM)
AW Active period, write access (XWRACTIVE + WS + 1) × t
c(XTIM)
(XWRACTIVE × 2 + WS + 1) × t
c(XTIM)
TW Trail period, write access XWRTRAIL × t
c(XTIM)
(XWRTRAIL × 2) × t
c(XTIM)
(1) t
c(XTIM)
− Cycle time, XTIMCLK
(2) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No
internal device hardware is included to detect illegal settings.
6.15.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then:
Lead: LR ≥ 2 × t
c(XTIM)
LW ≥ 3 × t
c(XTIM)
Active: AR ≥ 6 × t
c(XTIM)
AW ≥ 1 × t
c(XTIM)
Trail: TW ≥ 3 × t
c(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
≥ 2 ≥ 5 ≥ 0 ≥ 3
(1)
≥ 1 ≥ 3
(1)
0
(2)
(1) Lead and trail write must be at least 7.5 ns.
(2) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
Examples of valid and invalid timing when not sampling XREADY:
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
Invalid
(1)
0 0 0 0 0 0 0, 1
Valid
(2)
2 5 0 3 1 3 0
(3)
(1) No hardware to detect illegal XTIMING configurations
(2) Based on 300-MHz system clock speed.
(3) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
140 Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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