Datasheet

20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
16
14
13
12
SPISTE
(A)
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012 www.ti.com
C. In the slave mode, the SPISTE signal should be asserted low at least 1t
c(SPC)
(minimum) before the valid SPI clock
edge and remain low for at least 1t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6-19. SPI Slave Mode External Timing (Clock Phase = 0)
138 Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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