Datasheet

9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
8
5
3
2
1
SPISTE
(A)
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012 www.ti.com
A. In the master mode, SPISTE goes active 1t
c(SPC)
(minimum) before valid SPI clock edge. On the trailing end
of the word, the SPISTE will go inactive 1t
c(SPC)
after the receiving edge (SPICLK) of the last data bit, except
that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-17. SPI Master Mode External Timing (Clock Phase = 0)
134 Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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