Datasheet

t
d(IDLE−XCOL)
X1/X2
or XCLKIN
XCLKOUT
HALT HALT
Wake-up Latency
Flushing Pipeline
t
d(WAKE−HALT)
(A)
(B)
(C)
(D)
(E)
Device
Status
(F)
(H)
(G)
PLL Lock-up Time
Normal
Execution
t
w(WAKE-GPIO)
t
p
GPIOn
Oscillator Start-up Time
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
Table 6-17. HALT Mode Timing Requirements
MIN NOM MAX UNIT
t
w(WAKE-GPIO)
Pulse duration, GPIO wake-up signal t
oscst
+ 2t
c(OSCCLK)
(1)
cycles
t
w(WAKE-XRS)
Pulse duration, XRS wakeup signal t
oscst
+ 8t
c(OSCCLK)
cycles
(1) See Table 6-10 for an explanation of t
oscst
.
Table 6-18. HALT Mode Switching Characteristics
PARAMETER MIN TYP MAX UNIT
Delay time, IDLE instruction executed to
t
d(IDLE-XCOL)
32t
c(SCO)
45t
c(SCO)
cycles
XCLKOUT low
t
p
PLL lock-up time 2600t
c(OSCCLK)
cycles
Delay time, PLL lock to program execution resume
t
d(WAKE-HALT)
35t
c(SCO)
cycles
• Wake up from SARAM
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for 32 cycles before oscillator is turned off and the
CLKIN to the core is stopped. This delay enables the CPU pipeline and any other pending operations to flush
properly. If an access to XINTF is in progress and its access time is longer than this number then it will fail. It is
recommended to enter HALT mode from SARAM without an XINTF access in progress.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin
asynchronously begins the wakeup process, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 2,600 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles.
G. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the
interrupt (if enabled), after a latency.
H. Normal operation resumes.
Figure 6-13. HALT Wake-Up Using GPIOn
Copyright © 2009–2012, Texas Instruments Incorporated Electrical Specifications 127
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