Datasheet

t
h(boot-mode)
(A)
t
w(RSL2)
XCLKIN
X1/X2
XRS
Boot-Mode
Pins
XCLKOUT
I/O Pins
Address/Data/
Control
(Internal)
Boot-ROM Execution Starts
User-Code Execution Starts
User-Code Dependent
User-Code Execution Phase
(Don’t Care)
User-Code Dependent
User-Code Execution
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
GPIO Pins as Input
Peripheral/GPIO Function
t
d(EX)
OSCCLK * 5
OSCCLK/8
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com SPRS516D –MARCH 2009–REVISED AUGUST 2012
Table 6-10. Reset (XRS) Timing Requirements
MIN NOM MAX UNIT
t
w(RSL1)
(1)
Pulse duration, stable input clock to XRS high 64t
c(OSCCLK)
cycles
t
w(RSL2)
Pulse duration, XRS low Warm reset 64t
c(OSCCLK)
cycles
Pulse duration, reset pulse generated by
t
w(WDRS)
512t
c(OSCCLK)
cycles
watchdog
t
d(EX)
Delay time, address/data valid after XRS high 32t
c(OSCCLK)
cycles
t
OSCST
(2)
Oscillator start-up time 1 10 ms
t
h(boot-mode)
Hold time for boot-mode pins 200t
c(OSCCLK)
cycles
t
pup
Power-up time 5 ms
(1) In addition to the t
w(RSL1)
requirement, XRS has to be low until V
DD
has reached the minimum operating voltage.
(2) Dependent on crystal/resonator and board design.
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-6. Warm Reset
Copyright © 2009–2012, Texas Instruments Incorporated Electrical Specifications 121
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