Datasheet

t
w(RSL1)
t
h(boot-mode)
(B)
XCLKIN
X1/X2
XRS
Boot-Mode
Pins
V (1.2V/1.1V)
DD
XCLKOUT
I/OPins
User-CodeDependent
User-CodeDependent
Boot-ROMExecutionStarts
Peripheral/GPIOFunction
BasedonBootCode
GPIOPinsasInput
OSCCLK/64
(A)
GPIOPinsasInput(StateDependsonInternalPU/PD)
t
OSCST
User-CodeDependent
Address/Data/
Control
(Internal)
Address/DataValid.InternalBoot-ROMCodeExecutionPhase
User-CodeExecutionPhase
t
d(EX)
OSCCLK/16
V (3.3V)
DDIO
V (1.8V)
DD18
t
pup
(C)
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012 www.ti.com
A. Upon power up, SYSCLKOUT is OSCCLK/8. Since the XTIMCLK, CLKMODE, and BY4CLKMODE bits in the
XINTFCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 8 before it applies to
XCLKOUT. This explains why XCLKOUT = OSCCLK/64 during this phase. Subsequently, boot ROM changes
SYSCLKOUT to OSCLK/2. Because the XTIMCLK register is unchanged by the boot ROM, XCLKOUT is OSCCLK/16
during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
C. See Section 6.9 for requirements to ensure a high-impedance state for GPIO pins during power-up.
Figure 6-5. Power-on Reset
120 Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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TMS320C28341