Datasheet

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012 www.ti.com
Table 6-5. Clocking and Nomenclature (200-MHz Devices)
MIN NOM MAX UNIT
t
c(OSC)
, Cycle time 33.3 125 ns
On-chip oscillator clock (crystal/resonator–X1/X2)
Frequency 8 30 MHz
t
c(CI)
, Cycle time (C8) 6.67 50 ns
PLL enabled
Frequency 2 150 MHz
XCLKIN
(1)
t
c(CI)
, Cycle time (C8) 6.67 250 ns
PLL disabled
Frequency 4 150 MHz
t
c(CI)
, Cycle time (C8) 10 50 ns
PLL enabled
Frequency 2 100 MHz
X1
(1)
t
c(CI)
, Cycle time (C8) 10 250 ns
PLL disabled
Frequency 4 100 MHz
t
c(SCO)
, Cycle time 5 500 ns
SYSCLKOUT
Frequency 2 200 MHz
t
c(XCO)
, Cycle time 13.3 2000 ns
XCLKOUT
Frequency 0.5 75
(2)
MHz
t
c(HCO)
, Cycle time 8 ns
HSPCLK/EXTADCCLK
(3)
Frequency 40 MHz
t
c(LCO)
, Cycle time 10 20
(5)
ns
LSPCLK
(4)
Frequency 50
(5)
100 MHz
(1) The input clock frequency and PLLCR[DIV] values should be chosen such that the output frequency of the PLL(VCOCLK) lies between
400 MHz to 600 MHz.
(2) Although the maximum XCLKOUT frequency is 75 MHz, this value may not be attainable depending on SYSCLKOUT and available
prescalers.
(3) This frequency is limited by GPIO switching characteristics.
(4) Lower LSPCLK and HSPCLK will reduce device power consumption.
(5) This is the value if SYSCLKOUT = 200 MHz.
116 Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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TMS320C28341