Datasheet

CS
A(18:0)
OE
WE
D(15:0)
Low 16-bits
External
wait-state
generator
XREADY
XCLKOUT
XA(19:1)
XRD
XWE0
XD(15:0)
XINTF
CS
A(18:0)
OE
WE
D(31:16)
XWE1
XD(31:16)
XZCS0, XZCS6 XZCS7,
High 16-bits
XA(0)
X
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D –MARCH 2009–REVISED AUGUST 2012 www.ti.com
Figure 4-20. Typical 32-bit Data Bus XINTF Connections
Table 4-20. XINTF Configuration and Control Register Mapping
NAME ADDRESS SIZE (x16) DESCRIPTION
XTIMING0 0x00−0B20 2 XINTF Timing Register, Zone 0
XTIMING6
(1)
0x00−0B2C 2 XINTF Timing Register, Zone 6
XTIMING7 0x00−0B2E 2 XINTF Timing Register, Zone 7
XINTCNF2
(2)
0x00−0B34 2 XINTF Configuration Register
XBANK 0x00−0B38 1 XINTF Bank Control Register
XREVISION 0x00−0B3A 1 XINTF Revision Register
XRESET 0x00−0B3D 1 XINTF Reset Register
(1) XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used.
(2) XINTCNF1 is reserved and not currently used.
100 Peripherals Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,
TMS320C28341