Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesDigital signal processor (DSP) BGA 256 (17x17) 1.2 V 300 MHz

TMS320C28346, TMS320C28345, TMS320C28344

TMS320C28343, TMS320C28342, TMS320C28341

Delfino Microcontrollers

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SPRS516D

March 2009–Revised August 2012

Summary of content (170 pages)

PAGE 1
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Delfino Microcontrollers Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
PAGE 2
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Contents 1 TMS320C2834x ( Delfino™) MCUs 1.1 1.2 1.3 2 3 4 2 ....................................................................................... 10 Overview .................................................................................................................... 10 Features ............................................................................
PAGE 3
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 4.10 4.11 4.12 4.13 4.14 5 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) .......................................... Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D) ............................................................. Inter-Integrated Circuit (I2C) ............................................................................................. GPIO MUX ..........................
PAGE 4
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.16.2 McBSP as SPI Master or Slave Timing www.ti.com .................................................................... 160 7 8 Revision History .............................................................................................................. 164 Thermal and Mechanical Data ........................................................................................
PAGE 5
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 List of Figures .......................................... 2-1 C2834x 179-Ball ZHH MicroStar BGA™ Upper Left Quadrant (Bottom VIew) 2-2 C2834x 179-Ball ZHH MicroStar BGA™ Upper Right Quadrant (Bottom View) ......................................... 17 2-3 C2834x 179-Ball ZHH MicroStar BGA™ Lower Left Quadrant (Bottom View)...........................................
PAGE 6
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 6-6 Warm Reset ..................................................................................................................... 121 6-7 Example of Effect of Writing Into PLLCR Register ......................................................................... 122 6-8 General-Purpose Output Timing ..................................................................
PAGE 7
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 List of Tables .................................................................................................... 2-1 C2834x Hardware Features 2-2 Signal Descriptions ............................................................................................................... 23 3-1 Wait-states ...................................................................
PAGE 8
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com .......................................................................................... 6-10 Reset (XRS) Timing Requirements 6-11 General-Purpose Output Switching Characteristics ........................................................................ 122 6-12 .............................................................................. ........................
PAGE 9
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 8-1 Thermal Model 179-Ball ZHH Results 8-2 Thermal Model 256-Ball ZFE Results Copyright © 2009–2012, Texas Instruments Incorporated SPRS516D – MARCH 2009 – REVISED AUGUST 2012 ....................................................................................... .......................................................................................
PAGE 10
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Delfino Microcontrollers Check for Samples: TMS320C28346, TMS320C28345, TMS320C28344, TMS320C28343, TMS320C28342, TMS320C28341 1 TMS320C2834x ( Delfino™) MCUs 1.1 Overview The TMS320C2834x (C2834x) Delfino™ microcontroller (MCU) devices build on TI's existing F2833x high-performance floating-point microcontrollers.
PAGE 11
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 • Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug via Hardware 1.3 • 2834x Package Options: – MicroStar BGA™ (ZHH) – Plastic BGA (ZFE) Getting Started This section gives a brief overview of the steps to take when first developing for a C28x device.
PAGE 12
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 2 www.ti.com Introduction The TMS320C28346, TMS320C28345, TMS320C28344, TMS320C28343, TMS320C28342, and TMS320C28341 devices, members of the Delfino™ MCU generation, are highly integrated, highperformance solutions for demanding control applications. Throughout this document, the devices are abbreviated as C28346, C28345, C28344, C28343, C28342, and C28341, respectively.
PAGE 13
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 2-1. C2834x Hardware Features TYPE (1) C28346 (300 MHz) Package Type – 256-Ball ZFE PBGA (2) Instruction cycle – 3.33 ns 5 ns 3.33 ns 5 ns 3.
PAGE 14
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 2-1.
PAGE 15
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 2.1 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Pin Assignments The 179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 2-1 through Figure 2-4. The 256-ball ZFE plastic ball grid array (PBGA) terminal assignments are shown in Figure 2-5 through Figure 2-8. Table 2-2 describes the function(s) of each pin.
PAGE 16
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 P www.ti.
PAGE 17
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.
PAGE 18
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.
PAGE 19
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.
PAGE 20
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 9 10 www.ti.
PAGE 21
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.
PAGE 22
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.
PAGE 23
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 2.2 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Signal Descriptions Table 2-2 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs are not 5-V tolerant. All XINTF pins have a drive strength of 4 mA (typical).
PAGE 24
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 2-2. Signal Descriptions (continued) ZHH BALL # NAME ZFE BALL # DESCRIPTION Reset XRS P8 T10 Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC.
PAGE 25
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 2-2.
PAGE 26
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 2-2.
PAGE 27
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 2-2. Signal Descriptions (continued) ZHH BALL # ZFE BALL # GPIO37 ECAP2 XZCS7 D11 B12 General-Purpose Input/Output 37 (I/O/Z) Enhanced Capture input/output 2 (I/O) External Interface zone 7 chip select (O) GPIO38 XWE0 C12 E15 General-Purpose Input/Output 38 (I/O/Z) External Interface Write Enable 0 (O).
PAGE 28
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 2-2.
PAGE 29
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 2-2.
PAGE 30
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 2-2.
PAGE 31
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 2-2.
PAGE 32
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 2-2.
PAGE 33
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 2-2.
PAGE 34
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Functional Overview DMA Bus 3 www.ti.
PAGE 35
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 3.1 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Memory Maps In Figure 3-2 through Figure 3-4, the following apply: • Memory blocks are not to scale. • Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space.
PAGE 36
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Block Start Address www.ti.
PAGE 37
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.
PAGE 38
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Block Start Address www.ti.
PAGE 39
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written.
PAGE 40
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 3.2 3.2.1 www.ti.com Brief Descriptions C28x CPU The C2834x (C28x+FPU) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x MCUs, but also include a single-precision (32-bit) IEEE 754 floating-point unit (FPU).
PAGE 41
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 3.2.4 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Real-Time JTAG and Analysis The C2834x devices implement the standard IEEE 1149.1 JTAG interface. Additionally, the devices support real-time mode of operation whereby the contents of memory, peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts.
PAGE 42
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 3.2.8 www.ti.com Boot ROM The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal ROM.
PAGE 43
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 3.2.10 Peripheral Interrupt Expansion (PIE) Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the C2834x, 64 of the possible 96 interrupts are used by peripherals.
PAGE 44
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 3.2.16 Peripheral Frames 0, 1, 2, 3 (PFn) The device segregates peripherals into four sections.
PAGE 45
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 3.2.19 Control Peripherals The C2834x devices support the following peripherals which are used for embedded control and communication: ePWM: The enhanced PWM peripheral supports independent and complementary PWM generation, adjustable dead-band generation for leading and trailing edges, latched and cycle-by-cycle trip mechanism.
PAGE 46
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 3.3 www.ti.com Register Map The devices contain four peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 3-3. Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus. See Table 3-4.
PAGE 47
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 3-5.
PAGE 48
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 3.5 www.ti.com Interrupts Figure 3-5 shows how the various interrupt sources are multiplexed.
PAGE 49
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.
PAGE 50
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com IFR(12:1) INTM IER(12:1) INT1 INT2 1 CPU MUX 0 INT11 INT12 (Flag) Global Enable (Enable) INTx.1 INTx.2 INTx INTx.3 INTx.4 MUX INTx.5 INTx.6 From Peripherals or External Interrupts INTx.7 PIEACKx INTx.8 (Enable) (Flag) PIEIERx(8:1) PIEIFRx(8:1) (Enable/Flag) Figure 3-7. Multiplexing of Interrupts Using the PIE Block Table 3-8.
PAGE 51
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 3-9.
PAGE 52
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 3.5.1 www.ti.com External Interrupts Table 3-10.
PAGE 53
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 3.6 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 System Control This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. shows the various clock and reset domains that will be discussed.
PAGE 54
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-11. Table 3-11.
PAGE 55
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 The three possible input-clock configurations are shown in Figure 3-10 through Figure 3-12. XCLKIN VSSK X1 X2 NC External Clock Signal (Toggling 0 -VDDIO) Figure 3-10. Using a 3.3-V External Oscillator XCLKIN X1 X2 External Clock Signal (Toggling 0-VDD) NC Figure 3-11. Using a 1.8-V External Oscillator XCLKIN X1 X2 VSSK VDD18 Crystal 1.
PAGE 56
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 3.6.1.1 www.ti.com External Reference Oscillator Clock Option The on-chip oscillator requires an external crystal to be connected across the X1 and X2 pins. The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 3-12.
PAGE 57
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 3.6.1.2 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 PLL-Based Clock Module The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.
PAGE 58
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 3-14. Possible PLL Configuration Modes REMARKS PLLSTS[DIVSEL] (1) CLKIN AND SYSCLKOUT PLL Off Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block is disabled in this mode. This can be useful to reduce system noise and for low power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass) before entering this mode.
PAGE 59
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 3.6.2 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Watchdog Block The watchdog block on the C2834x device is similar to the one used on the 240x and 281x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value.
PAGE 60
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 3.7 www.ti.com Low-Power Modes Block The low-power modes on the C2834x devices are similar to the 240x devices. Table 3-15 summarizes the various modes. Table 3-15.
PAGE 61
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.
PAGE 62
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com L0 I/F L0 RAM L1 I/F L1 RAM L2 I/F L2 RAM L3 I/F L3 RAM L4 I/F L4 RAM L5 I/F L5 RAM L6 I/F L6 RAM L7 I/F L7 RAM INT7 External interrupts CPU timers PIE DINT[CH1:CH6] XINTF zones interface XINTF memory zones CPU bus McBSP A Event triggers PF3 I/F CPU DMA 6-ch McBSP B DMA bus Figure 4-1.
PAGE 63
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 4.2 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2 There are three 32-bit CPU-timers on the devices (CPU-Timer 0, CPU-Timer 1, CPU-Timer 2). Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0 and CPU-Timer 1 can be used in user applications. These timers are different from the timers that are present in the ePWM modules.
PAGE 64
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4-1 are used to configure the timers.
PAGE 65
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 4.3 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Enhanced PWM Modules The devices contain up to nine enhanced PWM (ePWM) modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7, ePWM8, ePWM9). Figure 4-4 shows a block diagram of multiple ePWM modules. Figure 4-5 shows the signal interconnections with the ePWM. Table 4-2 and Table 4-3 show the complete ePWM register set per module.
PAGE 66
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 4-2.
PAGE 67
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 4-3.
PAGE 68
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.
PAGE 69
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 4.4 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 High-Resolution PWM (HRPWM) The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be achieved using conventionally derived digital PWM methods.
PAGE 70
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 4.5 www.ti.com Enhanced CAP Modules The device contains up to six enhanced capture (eCAP) modules (eCAP1, eCAP2, eCAP3, eCAP4, eCAP5, and eCAP6). Figure 4-6 shows a functional block diagram of a module.
PAGE 71
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 The eCAP modules are clocked at the SYSCLKOUT rate. The clock enable bits (ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK, ECAP6ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power operation).
PAGE 72
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 4.6 www.ti.com Enhanced QEP Modules The device contains up to three enhanced quadrature encoder (eQEP) modules with 32-bit resolution (eQEP1, eQEP2, eQEP3). Figure 4-7 shows the block diagram of the eQEP module.
PAGE 73
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 4-5 provides a summary of the eQEP registers. Table 4-5.
PAGE 74
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.
PAGE 75
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 4.
PAGE 76
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Figure 4-9 shows the block diagram of the McBSP module.
PAGE 77
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 4-7 provides a summary of the McBSP registers. Table 4-7.
PAGE 78
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 4.9 www.ti.com Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) The CAN module has the following features: • Fully compliant with CAN protocol, version 2.
PAGE 79
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.
PAGE 80
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 4-8. 3.3-V eCAN Transceivers PART NUMBER SUPPLY VOLTAGE LOW-POWER MODE SLOPE CONTROL VREF OTHER TA SN65HVD230Q 3.3 V Standby Adjustable Yes – –40°C to 125°C SN65HVD231Q 3.3 V Sleep Adjustable Yes – –40°C to 125°C SN65HVD232Q 3.3 V None None None – –40°C to 125°C SN65HVD233 3.
PAGE 81
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.
PAGE 82
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.
PAGE 83
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 The CAN registers listed in Table 4-9 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary. Table 4-9.
PAGE 84
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) The devices include three serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero (NRZ) format.
PAGE 85
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Enhanced features: • Auto baud-detect hardware logic • 16-level transmit/receive FIFO The SCI port operation is configured and controlled by the registers listed in Table 4-10, Table 4-11, and Table 4-12. Table 4-10.
PAGE 86
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 4-12.
PAGE 87
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Figure 4-13 shows the SCI module block diagram. SCICTL1.1 Frame Format and Mode SCITXD TXSHF Register Parity Even/Odd Enable TX EMPTY SCICTL2.6 8 SCICCR.6 SCICCR.5 TXRDY SCICTL2.7 Transmitter-Data Buffer Register TXWAKE SCICTL1.3 SCICTL2.0 TXINT TX FIFO _0 TX Interrupt Logic TX FIFO _1 WUT ----- TX FIFO _15 TX FIFO Interrupts SCITXBUF.
PAGE 88
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 4.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D) The device includes the four-pin serial peripheral interface (SPI) module. Two SPI modules (SPI-A and SPI-D) are available.
PAGE 89
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Enhanced features: • 16-level transmit/receive FIFO • Delayed transmit control The SPI port operation is configured and controlled by the registers listed in Table 4-13 and Table 4-14 . Table 4-13.
PAGE 90
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Figure 4-14 is a block diagram of the SPI in slave mode. SPIFFENA Overrun INT ENA Receiver Overrun Flag SPIFFTX.14 RX FIFO registers SPISTS.7 SPICTL.4 SPIRXBUF RX FIFO _0 RX FIFO _1 SPIINT/SPIRXINT RX FIFO Interrupt −−−−− RX Interrupt Logic RX FIFO _15 16 SPIRXBUF Buffer Register SPIFFOVF FLAG SPIFFRX.
PAGE 91
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 4.12 Inter-Integrated Circuit (I2C) The device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral module interfaces within the device. System Control Block C28x CPU I2CAENCLK SYSRS Control Data[16] SDAA Peripheral Bus SYSCLKOUT Data[16] 2 GPIO MUX I C-A Addr[16] SCLA I2CINT1A I2CINT2A A. B.
PAGE 92
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 • • • • www.ti.com One interrupt that can be used by the CPU.
PAGE 93
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.
PAGE 94
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-16 shows the GPIO register mapping. Table 4-16.
PAGE 95
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 4-16. GPIO Registers (continued) NAME ADDRESS SIZE (x16) GPIOXINT6SEL 0x6FE6 1 XINT6 GPIO Input Select Register (GPIO32 to 63) DESCRIPTION GPIOINT7SEL 0x6FE7 1 XINT7 GPIO Input Select Register (GPIO32 to 63) GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31) Reserved 0x6FEA – 0x6FFF 22 Table 4-17.
PAGE 96
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 4-18.
PAGE 97
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 4-19.
PAGE 98
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices: • Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
PAGE 99
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 4.14 External Interface (XINTF) This section gives a top-level view of the external interface (XINTF) that is implemented on the C2834x devices. The XINTF is a non-multiplexed asynchronous bus, similar to the 2812 XINTF. The XINTF is mapped into three fixed zones shown in Figure 4-18.
PAGE 100
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com XINTF External wait-state generator Low 16-bits CS A(18:0) OE WE D(15:0) XREADY XCLKOUT X XA(0) XA(19:1) XRD XWE0 XD(15:0) High 16-bits A(18:0) XZCS0, XZCS6, XZCS7 CS OE WE XWE1 D(31:16) XD(31:16) Figure 4-20. Typical 32-bit Data Bus XINTF Connections Table 4-20.
PAGE 101
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 5 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Device Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
PAGE 102
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
PAGE 103
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 5.2 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Documentation Support Extensive documentation supports all of the TMS320™ DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications.
PAGE 104
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com SPRUFN5 TMS320x2834x Delfino Boot ROM Reference Guide. This document describes the purpose and features of the bootloader (factory-programmed boot-loading software) and provides examples of code. It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory.
PAGE 105
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 SPRU608 TMS320C28x Instruction Set Simulator Technical Overview. This document describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x™ core. SPRU625 TMS320C28x DSP/BIOS 5.32 Application Programming Interface (API) Reference Guide. This document describes development using DSP/BIOS.
PAGE 106
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com SPRA820 Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for online stack overflow detection on the TMS320C28x™ DSP. C-source code is provided that contains functions for implementing the overflow detection on both DSP/BIOS™ and nonDSP/BIOS applications.
PAGE 107
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 6 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions. 6.1 Absolute Maximum Ratings (1) (2) Supply voltage range, VDDIO with respect to VSS –0.3 V to 4.0 V Supply voltage range, VDD with respect to VSS –0.3 V to 1.5 V Supply voltage range, VDD18 with respect to VSS –0.3 V to 2.
PAGE 108
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.2 www.ti.com Recommended Operating Conditions MIN NOM MAX UNIT 3.14 3.3 3.46 V 300-MHz devices 1.14 1.2 1.26 V 200-MHz devices 1.05 1.1 1.16 V Device supply voltage, I/O, VDDIO Device supply voltage CPU, VDD Supply ground, VSS, VSSIO 0 Oscillator supply ground, VSSK V 0 PLL/oscillator supply, VDD18 1.
PAGE 109
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 6.4 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Current Consumption Table 6-1.
PAGE 110
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 6-2.
PAGE 111
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 6.4.1 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Reducing Current Consumption Methods of reducing current consumption include the following: • Turn off the clock to any peripheral module that is not used in a given application since each peripheral unit has an individual clock-enable bit. Table 6-3 indicates the typical reduction in current consumption achieved by turning off the clocks.
PAGE 112
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 6-3. Typical Current Consumption by Various Peripherals (1) (1) (2) 112 Electrical Specifications PERIPHERAL MODULE IDD CURRENT REDUCTION (mA) I2C 5 eQEP 5 ePWM 3 eCAP 1 SCI 4 SPI 4 eCAN 2 McBSP 8 CPU-Timer 1 XINTF 4 (2) DMA 7 FPU 8 All peripheral clocks (except CPU timer clocks) are disabled upon reset.
PAGE 113
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 6.5 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Thermal Design Considerations Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design.
PAGE 114
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.7 www.ti.com Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: 6.7.
PAGE 115
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 6.7.3 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available. Table 6-4 through Table 6-5 list the cycle times of various clocks. Table 6-4.
PAGE 116
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 6-5. Clocking and Nomenclature (200-MHz Devices) MIN On-chip oscillator clock (crystal/resonator–X1/X2) PLL enabled XCLKIN (1) PLL disabled PLL enabled X1 (1) PLL disabled SYSCLKOUT 116 Frequency tc(CI), Cycle time (C8) Frequency tc(CI), Cycle time (C8) Frequency MAX UNIT 33.3 125 ns 8 30 MHz 6.67 50 ns 2 150 MHz 6.
PAGE 117
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 6.8 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Clock Requirements and Characteristics Table 6-6. XCLKIN/X1 Timing Requirements – PLL Enabled NO.
PAGE 118
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.9 www.ti.com Power Sequencing No special requirements are placed on the power up/down sequence of the various power pins to ensure the correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of the I/O pins are powered prior to the 1.1-V/1.
PAGE 119
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 6.9.1 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Power Management and Supervisory Circuit Solutions Table 6-9 lists the power management and supervisory circuit solutions for the 2834x devices. LDO selection depends on the total power consumed in the end application. Go to www.ti.
PAGE 120
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com VDDIO (3.3 V) VDD18 (1.8 V) VDD (1.2 V/1.1 V) tpup XCLKIN X1/X2 OSCCLK/64 (A) XCLKOUT tOSCST OSCCLK/16 User-Code Dependent tw(RSL1) XRS Address/Data Valid.
PAGE 121
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 6-10.
PAGE 122
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Figure 6-7 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0003 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0007 (setting for OSCCLK x 8). Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2.
PAGE 123
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 6.10.2 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 GPIO - Input Timing (A) GPIO Signal GPxQSELn = 1,0 (6 samples) 1 1 0 0 0 0 0 0 0 1 0 tw(SP) 0 0 1 1 1 1 1 1 1 1 1 Sampling Period determined by GPxCTRL[QUALPRD](B) tw(IQSW) (SYSCLKOUT cycle * 2 * QUALPRD) * 5(C)) Sampling Window SYSCLKOUT QUALPRD = 1 (SYSCLKOUT/2) (D) Output From Qualifier A. B. C. D.
PAGE 124
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 6.10.3 Sampling Window Width for Input Signals The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
PAGE 125
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.10.4 Low-Power Mode Wakeup Timing The wakeup signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
PAGE 126
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 6-15. STANDBY Mode Timing Requirements tw(WAKE-INT) (1) Pulse duration, external wake-up signal TEST CONDITIONS MIN Without input qualification 3tc(OSCCLK) With input qualification (1) NOM MAX UNIT cycles (2 + QUALSTDBY) * tc(OSCCLK) QUALSTDBY is a 6-bit field in the LPMCR0 register. Table 6-16.
PAGE 127
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 6-17. HALT Mode Timing Requirements MIN tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal tw(WAKE-XRS) Pulse duration, XRS wakeup signal (1) NOM MAX UNIT (1) cycles toscst + 8tc(OSCCLK) cycles toscst + 2tc(OSCCLK) See Table 6-10 for an explanation of toscst. Table 6-18.
PAGE 128
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 6.11 Enhanced Control Peripherals 6.11.1 Enhanced Pulse Width Modulator (ePWM) Timing PWM refers to PWM outputs on ePWM1–6. Table 6-19 shows the PWM timing requirements and Table 620, switching characteristics. Table 6-19.
PAGE 129
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.11.3 High-Resolution PWM Timing Table 6-22 shows the high-resolution PWM switching characteristics. Table 6-22. High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz) MIN Micro Edge Positioning (MEP) step size (1) (1) TYP MAX UNIT VDD = 1.2 V 55 120 ps VDD = 1.
PAGE 130
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 6.11.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing Table 6-25 shows the eQEP timing requirement and Table 6-26 shows the eQEP switching characteristics. Table 6-25.
PAGE 131
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.11.6 ADC Start-of-Conversion Timing Table 6-27. External ADC Start-of-Conversion Switching Characteristics PARAMETER tw(ADCSOCL) MIN Pulse duration, ADCSOCxO low MAX 32tc(HCO ) UNIT cycles tw(ADCSOCL) ADCSOCAO or ADCSOCBO Figure 6-15. ADCSOCAO or ADCSOCBO Timing 6.
PAGE 132
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 6.13 I2C Electrical Specification and Timing Table 6-30.
PAGE 133
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 6-31. SPI Master Mode External Timing (Clock Phase = 0) (1) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. UNIT MIN MAX MIN MAX 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns ns tc(SPC)M Cycle time, SPICLK 2 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.
PAGE 134
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 SPISOMI Master In Data Must Be Valid SPISTE(A) A. In the master mode, SPISTE goes active 1tc(SPC) (minimum) before valid SPI clock edge.
PAGE 135
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 6-32. SPI Master Mode External Timing (Clock Phase = 1) (1) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. UNIT MIN MAX MIN MAX 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns ns tc(SPC)M Cycle time, SPICLK 2 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.
PAGE 136
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 SPISIMO Master Out Data Is Valid Data Valid 10 11 SPISOMI Master In Data Must Be Valid SPISTE(A) B. In the master mode, SPISTE goes active 1tc(SPC) (minimum) before valid SPI clock edge.
PAGE 137
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.14.2 SPI Slave Mode Timing Table 6-33 lists the slave mode external timing (clock phase = 0) and Table 6-34 (clock phase = 1). Figure 6-19 and Figure 6-20 show the timing waveforms. Table 6-33. SPI Slave Mode External Timing (Clock Phase = 0) (1) NO.
PAGE 138
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 15 16 SPISOMI SPISOMI Data Is Valid 19 20 SPISIMO SPISIMO Data Must Be Valid SPISTE(A) C. In the slave mode, the SPISTE signal should be asserted low at least 1tc(SPC) (minimum) before the valid SPI clock edge and remain low for at least 1tc(SPC) after the receiving edge (SPICLK) of the last data bit.
PAGE 139
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 6-34. SPI Slave Mode External Timing (Clock Phase = 1) (1) NO. (2) (3) (4) MIN MAX 12 tc(SPC)S Cycle time, SPICLK 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.
PAGE 140
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 6.15 External Interface (XINTF) Timing Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone.
PAGE 141
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.15.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then: 1 Lead: LR ≥ 2 × tc(XTIM) LW ≥ 3 × tc(XTIM) 2 Active: AR ≥ 6 × tc(XTIM) AW ≥ 2 × tc(XTIM) 3 Trail: TW ≥ 3 × tc(XTIM) NOTE Restriction does not include external hardware wait states.
PAGE 142
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 6.15.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then: 1 LR ≥ 2 × tc(XTIM) Lead: LW ≥ 3 × tc(XTIM) 2 AR ≥ 6 × tc(XTIM) Active: AW ≥ 4 × tc(XTIM) 3 TW ≥ 3 × tc(XTIM) Trail: NOTE Restrictions do not include external hardware wait states.
PAGE 143
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-36. Table 6-36.
PAGE 144
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 6.15.4 XINTF Signal Alignment to XCLKOUT For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK. Strobes such as XRD, XWE0, XWE1, and zone chip-select (XZCS) change state in relationship to the rising edge of XTIMCLK.
PAGE 145
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.15.5 External Interface Read Timing Table 6-37.
PAGE 146
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com (A)(B) Trail Active Lead (C) (D) XCLKOUT = XTIMCLK td(XCOH-XZCSL) td(XCOHL-XZCSH) XZCS0, XZCS6, XZCS7 td(XCOH-XA) XA[0:19] td(XCOHL-XRDH) td(XCOHL-XRDL) XRD (E) XWE, XWE1 tsu(XD)XRD XR/W ta(A) th(XD)XRD ta(XRD) XD[0:31], XD[0:15] XREADY A. B. C. D. E. F. DIN (F) All XINTF accesses (lead period) begin on the rising edge of XCLKOUT.
PAGE 147
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.15.6 External Interface Write Timing Table 6-39. External Interface Write Switching Characteristics PARAMETER MIN MAX 0 2 ns –0.2 0.9 ns 1.5 ns –0.3 0.7 ns Delay time, XCLKOUT high/low to XWE0, XWE1 high –0.5 0.5 ns Delay time, XCLKOUT high to XR/W low –0.2 1.5 ns 0.3 0.
PAGE 148
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 (A) (B) www.ti.com Active Lead (C) Trail (D) XCLKOUT = XTIMCLK td(XCOHL-XZCSH) td(XCOH-XZCSL) XZCS0, XZCS6, XZCS7 td(XCOH-XA) XA[0:19] XRD td(XCOHL-XWEH) td(XCOHL-XWEL) (E) XWE0, XWE1 A. B. C. D. E. F.
PAGE 149
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.15.7 External Interface Ready-on-Read Timing With One External Wait State Table 6-40. External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) PARAMETER MIN MAX 0 2 UNIT ns –0.2 0.9 ns 1.5 ns –0.2 0.8 ns –0.4 0.
PAGE 150
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.
PAGE 151
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.
PAGE 152
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 6.15.8 External Interface Ready-on-Write Timing With One External Wait State Table 6-44.
PAGE 153
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.
PAGE 154
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.
PAGE 155
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 6.15.9 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 XHOLD and XHOLDA Timing If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of high-impedance mode. On a reset (XRS), the HOLD mode bit is set to 0.
PAGE 156
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com XCLKOUT td(HL-Hiz) XHOLD td(HH-HAH) XHOLDA td(HL-HAL) td(HH-BV) XR/W High-Impedance XZCS0, XZCS6, XZCS7 XA[19:0] Valid XD[31:0], XD[15:0] Valid (A) A. B. Valid High-Impedance (B) All pending XINTF accesses are completed. Normal XINTF operation resumes. Figure 6-28.
PAGE 157
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 6.16 Multichannel Buffered Serial Port (McBSP) Timing 6.16.1 McBSP Transmit and Receive Timing Table 6-48. McBSP Timing Requirements (1) (2) NO.
PAGE 158
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 6-49. McBSP Switching Characteristics (1) NO.
PAGE 159
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 M1, M11 M2, M12 M13 M3, M12 CLKR M4 M4 M14 FSR (int) M15 M16 FSR (ext) M18 M17 DR (RDATDLY=00b) Bit (n−1) (n−2) (n−3) M17 (n−4) M18 DR (RDATDLY=01b) Bit (n−1) (n−2) (n−3) M17 M18 DR (RDATDLY=10b) Bit (n−1) (n−2) Figure 6-29.
PAGE 160
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com 6.16.2 McBSP as SPI Master or Slave Timing Table 6-50. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) NO.
PAGE 161
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 6-52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) MASTER NO.
PAGE 162
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 www.ti.com Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) NO.
PAGE 163
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) MASTER NO.
PAGE 164
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 7 www.ti.com Revision History This data sheet revision history highlights the technical changes made to the SPRS516C device-specific data sheet to make it an SPRS516D revision. Scope: See table below. LOCATION 164 ADDITIONS, DELETIONS, AND MODIFICATIONS Section 1.2 Features: • Added "Endianness: Little Endian" feature Section 6.
PAGE 165
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com 8 SPRS516D – MARCH 2009 – REVISED AUGUST 2012 Thermal and Mechanical Data Table 8-1 and Table 8-2 show the thermal data. The mechanical package diagrams that follow the tables reflect the most current released mechanical data available for the designated devices. Table 8-1. Thermal Model 179-Ball ZHH Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA[°C/W] High k PCB 40.8 32.4 31.0 29.
PAGE 166
PACKAGE OPTION ADDENDUM www.ti.
PAGE 167
PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2012 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
PAGE 168
PAGE 169
PAGE 170
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.