Datasheet

HIGH-SPEED MODE
UNDERVOLTAGE LOCKOUT
TIMEOUT FUNCTION
GENERAL CALL RESET
SHUTDOWN MODE (SD)
FILTERING
SENSOR FAULT
TMP441
TMP442
SBOS425A DECEMBER 2008 REVISED MARCH 2009 ..............................................................................................................................................
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When not using the remote sensor with the
TMP441/42, the DXP and DXN inputs must be
In order for the Two-Wire bus to operate at
connected together to prevent meaningless fault
frequencies above 400kHz, the master device must
warnings.
issue a High-Speed mode (Hs-mode) master code
(0000 1xxx) as the first byte after a START condition
to switch the bus to high-speed operation. The
TMP441/42 acknowledge this byte, but switch the
The TMP441/42 sense when the power-supply
input filters on SDA and SCL and the output filter on
voltage has reached a minimum voltage level for the
SDA to operate in Hs-mode, allowing transfers at up
ADC to function. The detection circuitry consists of a
to 3.4MHz. After the Hs-mode master code has been
voltage comparator that enables the ADC after the
issued, the master transmits a Two-Wire slave
power supply (V+) exceeds 2.45V (typical). The
address to initiate a data transfer operation. The bus
comparator output is continuously checked during a
continues to operate in Hs-mode until a STOP
conversion. The TMP441/42 do not perform a
condition occurs on the bus. Upon receiving the
temperature conversion if the power supply is not
STOP condition, the TMP441/42 switch the input and
valid. The PVLD bit (bit 1, see Table 3 ) of the
output filters back to fast mode operation.
Local/Remote Temperature Register is set to '1' and
the temperature result may be incorrect.
The TMP441/42 reset the serial interface if either
SCL or SDA are held low for 32ms (typical) between
The TMP441/42 support reset via the Two-Wire
a START and STOP condition. If the TMP441/42 are
General Call address 00h (0000 0000b). The
holding the bus low, they release the bus and waits
TMP441/42 acknowledge the General Call address
for a START condition. To avoid activating the
and respond to the second byte. If the second byte is
timeout function, it is necessary to maintain a
06h (0000 0110b), the TMP441/42 execute a
communication speed of at least 1kHz for the SCL
software reset. This software reset restores the
operating frequency.
power-on reset state to all TMP441/42 registers, and
aborts any conversion in progress. The TMP441/42
take no action in response to other values in the
second byte.
The TMP441/42 Shutdown Mode allows maximum
power to be saved by shutting down all device
circuitry other than the serial interface, reducing
current consumption to typically less than 3 µ A; see
Remote junction temperature sensors are usually
Figure 6 , Shutdown Quiescent Current vs Supply
implemented in a noisy environment. Noise is
Voltage. Shutdown Mode is enabled when the SD bit
frequently generated by fast digital signals and if not
of the Configuration Register is high; the device shuts
filtered properly will induce errors that can corrupt
down once the current conversion is completed.
temperature measurements. The TMP441/42 have a
When SD is low, the device maintains a continuous
built-in 65kHz filter on the inputs of DXP and DXN to
conversion state.
minimize the effects of noise. However, a differential
low-pass filter can help attenuate unwanted coupled
signals. If filtering is needed, suggested component
values are 100pF and 50 on each input; exact
The TMP441/42 can sense a fault at the DXP input
values are application-specific. It is also
resulting from incorrect diode connection and can
recommended that the capacitor value remains
sense an open circuit. Short-circuit conditions return a
between 0pF to 330pF with a series resistance less
value of 64 ° C. The detection circuitry consists of a
than 1k .
voltage comparator that trips when the voltage at
DXP exceeds (V+) 0.6V (typical). The comparator
output is continuously checked during a conversion. If
a fault is detected, the OPEN bit (bit 0) in the
temperature result register is set to '1' and the rest of
the register bits should be ignored.
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