Datasheet

TIMING DIAGRAMS
SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BUF)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
P S S P
TMP441
TMP442
www.ti.com .............................................................................................................................................. SBOS425A – DECEMBER 2008 – REVISED MARCH 2009
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not
The TMP441/42 are Two-Wire and
limited and is determined by the master device. The
SMBus-compatible. Figure 15 to Figure 18 describe
receiver acknowledges data transfer.
the various operations on the TMP441/42.
Parameters for Figure 15 are defined in Table 11 . Acknowledge: Each receiving device, when
Bus definitions are: addressed, is obliged to generate an Acknowledge
bit. A device that acknowledges must pull down the
Bus Idle: Both SDA and SCL lines remain high.
SDA line during the Acknowledge clock pulse in such
a way that the SDA line is stable low during the high
Start Data Transfer: A change in the state of the
period of the Acknowledge clock pulse. Setup and
SDA line, from high to low, while the SCL line is high,
hold times must be taken into account. On a master
defines a START condition. Each data transfer is
receive, data transfer termination can be signaled by
initiated with a START condition.
the master generating a Not-Acknowledge on the last
Stop Data Transfer: A change in the state of the
byte that has been transmitted by the slave.
SDA line from low to high while the SCL line is high
defines a STOP condition. Each data transfer
terminates with a repeated START or STOP
condition.
Figure 15. Two-Wire Timing Diagram
Table 11. Timing Characteristics for Figure 15
FAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX UNIT
SCL operating frequency f
(SCL)
0.001 0.4 0.001 3.4 MHz
Bus free time between STOP and START conditions t
(BUF)
600 160 ns
Hold time after repeated START condition. After this period, the first clock
t
(HDSTA)
100 100 ns
is generated.
Repeated START condition setup time t
(SUSTA)
100 100 ns
STOP condition setup time t
(SUSTO)
100 100 ns
Data hold time t
(HDDAT)
0 0 ns
Data setup time t
(SUDAT)
100 10 ns
SCL clock LOW period t
(LOW)
1300 160 ns
SCL clock HIGH period t
(HIGH)
600 60 ns
Clock/Data fall time t
F
300 160 ns
Clock/Data rise time t
R
300 160 ns
for SCL ≤ 100kHz t
R
1000 ns
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