Datasheet

BUS OVERVIEW
READ/WRITE OPERATIONS
SERIAL INTERFACE
SERIAL BUS ADDRESS
TWO-WIRE INTERFACE SLAVE DEVICE
TMP441
TMP442
SBOS425A – DECEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com
Table 10. TMP441 Slave Address Options
TWO-WIRE SLAVE
The TMP441/42 are SMBus interface-compatible. In
ADDRESS A1 A0
SMBus protocol, the device that initiates the transfer
0011 100 Float 0
is called a master, and the devices controlled by the
master are slaves. The bus must be controlled by a 0011 101 Float 1
master device that generates the serial clock (SCL),
0011 110 0 Float
controls the bus access, and generates the START
0011 111 1 Float
and STOP conditions.
0101 010 Float Float
To address a specific device, a START condition is
1001 100 0 0
initiated. START is indicated by pulling the data line
1001 101 0 1
(SDA) from a high-to-low logic level while SCL is
1001 110 1 0
high. All slaves on the bus shift in the slave address
1001 111 1 1
byte, with the last bit indicating whether a read or
write operation is intended. During the ninth clock
The TMP442 has a factory-preset slave address. The
pulse, the slave being addressed responds to the
TMP442A slave address is 1001100b, and the
master by generating an Acknowledge and pulling
TMP442B slave address is 1001101b. The
SDA low.
configuration of the DXP and DXN channels are
Data transfer is then initiated and sent over eight
independent of the address. Unused DXP channels
clock pulses followed by an Acknowledge bit. During
can be left open or tied to GND.
data transfer SDA must remain stable while SCL is
high, because any change in SDA while SCL is high
is interpreted as a control signal.
Accessing a particular register on the TMP441/42 is
Once all data have been transferred, the master
accomplished by writing the appropriate value to the
generates a STOP condition. STOP is indicated by
Pointer Register. The value for the Pointer Register is
pulling SDA from low to high, while SCL is high.
the first byte transferred after the slave address byte
with the R/ W bit low. Every write operation to the
TMP441/42 requires a value for the Pointer Register
(see Figure 16 ).
The TMP441/42 operate only as a slave device on
either the Two-Wire bus or the SMBus. Connections
When reading from the TMP441/42, the last value
to either bus are made via the open-drain I/O lines,
stored in the Pointer Register by a write operation is
SDA and SCL. The SDA and SCL pins feature
used to determine which register is read by a read
integrated spike suppression filters and Schmitt
operation. To change the register pointer for a read
triggers to minimize the effects of input spikes and
operation, a new value must be written to the Pointer
bus noise. The TMP441/42 support the transmission
Register. This transaction is accomplished by issuing
protocol for fast (1kHz to 400kHz) and high-speed
a slave address byte with the R/ W bit low, followed
(1kHz to 3.4MHz) modes. All data bytes are
by the Pointer Register byte; no additional data are
transmitted MSB first.
required. The master can then generate a START
condition and send the slave address byte with the
R/ W bit high to initiate the read command. See
Figure 18 for details of this sequence. If repeated
To communicate with the TMP441/42, the master
reads from the same register are desired, it is not
must first address slave devices via a slave address
necessary to continually send the Pointer Register
byte. The slave address byte consists of seven
bytes, because the TMP441/42 retain the Pointer
address bits, and a direction bit indicating the intent
Register value until it is changed by the next write
of executing a read or write operation.
operation. Note that register bytes are sent MSB first,
followed by the LSB.
ADDRESSES Read operations should be terminated by issuing a
Not-Acknowledge command at the end of the last
The TMP441 supports nine slave device addresses.
byte to be read. For a single-byte operation, the
The TMP442A and TMP442B are available in two
master should leave the SDA line high during the
different fixed serial interface addresses.
Acknowledge time of the first byte that is read from
the slave. For a two-byte read operation, the master
The slave device address for the TMP441 is set by
must pull SDA low during the Acknowledge time of
the A1 and A0 pins, as summarized in Table 10 .
the first byte read, and should leave SDA high during
the Acknowledge time of the second byte read from
the slave.
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