Datasheet
Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address Byte
Start By
Master
ACK By
TMP431A/32A/31C
From
TMP431A/32A/31C
NACK By
Master
Stop By
Master
1 9 1
9
SDA
SCL
ALERT
0 0 0 1 1 0 0 R/W
1 0 0 1 1 0 0
(1)
Status
NOTE (1): Slave address 1001100 (TMP431A/32A/31C) shown. Slave address changes for TMP431B/32B/31D. See table for more details.Ordering Information
Frame 1 Two-Wire Slave Address Byte Frame 2 Pointer Register Byte
1
Start By
Master
ACK By
TMP431 A/31CA/32
ACK By
TMP431 A/31CA/32
Frame 3 Two-Wire Slave Address Byte Frame 4 Data Byte 1 Read Register
Start By
Master
ACK By
TMP431 A/31CA/32
ACK By
Master
From
TMP431 A/31CA/32
1 9 1
9
1 9 1 9
SDA
SCL
0 0 1 R/W
P7 P6 P5 P4 P3 P2 P1 P0
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
1 0 0 1
1 0 0
(1)
1 0 0
(1)
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Frame 5 Data Byte 2 Read Register
Stop By
Master
NACK By
Master
(2)
From
TMP431 A/31CA/32
1 9
D7 D6 D5 D4 D3 D2 D1 D0
(1) Slave address 1001100 (TMP431A/32A/31C) shown. Slave address changes for TMP431B/32B/31D. See table for more details.Ordering Information
(2) Master should leave SDA high to terminate a two-byte read operation.
NOTES:
TMP431
TMP432
SBOS441F –SEPTEMBER 2009–REVISED AUGUST 2013
www.ti.com
Figure 21. Two-Wire Timing Diagram for Two-Byte Read Format
Figure 22. Timing Diagram for SMBus ALERT
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