Datasheet

SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BUF)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
P S S P
TMP431
TMP432
SBOS441F –SEPTEMBER 2009–REVISED AUGUST 2013 www.ti.com
TIMING DIAGRAMS Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not
The TMP431/32 are Two-Wire and SMBus-
limited and is determined by the master device. The
compatible. Figure 18 to Figure 22 describe the
receiver acknowledges the transfer of data.
various operations on the TMP431/32. Bus definitions
are given below. Parameters for Figure 18 are Acknowledge: Each receiving device, when
defined in Table 16. addressed, is obliged to generate an Acknowledge
bit. A device that acknowledges must pull down the
Bus Idle: Both SDA and SCL lines remain high.
SDA line during the Acknowledge clock pulse in such
a way that the SDA line is stable low during the high
Start Data Transfer: A change in the state of the
SDA line, from high to low, while the SCL line is high,
period of the Acknowledge clock pulse. Setup and
defines a START condition. Each data transfer is
hold times must be taken into account. On a master
initiated with a START condition.
receive, data transfer termination can be signaled by
the master generating a Not-Acknowledge on the last
Stop Data Transfer: A change in the state of the
byte that has been transmitted by the slave.
SDA line from low to high while the SCL line is high
defines a STOP condition. Each data transfer
terminates with a STOP or a repeated START
condition.
Figure 18. Two-Wire Timing Diagram
Table 16. Timing Diagram Definitions for Figure 18
FAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX UNITS
SCL Operating Frequency f
(SCL)
0.001 0.4 0.001 3.4 MHZ
Bus Free Time Between STOP ns
t
(BUF)
600 160
and START Condition
Hold time after repeated START
condition. After this period, the t
(HDSTA)
100 100 ns
first clock is generated.
Repeated START Condition Setup
t
(SUSTA)
100 100 ns
Time
STOP Condition Setup Time t
(SUSTO)
100 100 ns
Data Hold Time t
(HDDAT)
0
(1)
0
(2)
ns
Data Setup Time t
(SUDAT)
100 10 ns
SCL Clock LOW Period t
(LOW)
1300 160 ns
SCL Clock HIGH Period t
(HIGH)
600 60 ns
Clock/Data Fall Time t
F
300 160 ns
Clock/Data Rise Time 300 160 ns
t
R
for SCLK ≤ 100kHz 1000 ns
(1) For cases with fall time of SCL less than 20ns and/or the rise time or fall time of SDA less than 20ns, the hold time should be greater
than 20ns.
(2) For cases with fall time of SCL less than 10ns and/or the rise or fall time of SDA less than 10ns, the hold time should be greater than
10ns.
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