Datasheet

V+
DXP
DXN
GND
GroundorV+layer
onbottomand/or
top,ifpossible.
1
2
3
4
8
7
6
5
TMP421
0.1mFCapacitor
V+
GND
PCBVia
DXP
DXN
A1
A0
1
2
3
4
8
7
6
5
TMP422
0.1mFCapacitor
V+
GND
PCBVia
DX1
DX2
DX3
DX4
1
2
3
4
8
7
6
5
TMP423
0.1mFCapacitor
V+
GND
PCBVia
DXP1
DXP2
DXP3
DXN
TMP421C
0.1mFCapacitor
V+
GND
PCBVia
DXP
DXN
A1
A0
1
2
8
7
3
4
6
5
TMP421
TMP422
TMP423
www.ti.com SBOS398C –JULY 2007–REVISED MAY 2012
NOTE: Use minimum 5 mil (0.127mm) traces with 5 mil spacing.
Figure 20. Suggested PCB Layer Cross-Section
Figure 21. Suggested Bypass Capacitor Placement and Trace Shielding
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Product Folder Link(s): TMP421 TMP422 TMP423