Datasheet

Frame1Two-WireSlaveAddressByte Frame2PointerRegisterByte
1
StartBy
Master
ACKBy
TMP421/22/23
ACKBy
TMP421/22/23
Frame3Two-WireSlaveAddressByte Frame4DataByte1ReadRegister
StartBy
Master
ACKBy
TMP421/22/23
ACKBy
Master
From
TMP421/22/23
1 9 1
9
1 9 1
9
SDA
SCL
0 0 1 R/
W P7 P6 P5 P4 P3 P2 P1 P0
¼
¼
¼
¼
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
1 0 0 1
1 0 0
(1)
1 0 0
(1)
R/
W D7 D6 D5 D4 D3 D2 D1 D0
Frame5DataByte2ReadRegister
StopBy
Master
NACKBy
Master
(2)
From
TMP421/22/23
1
9
D7 D6 D5 D4 D3 D2 D1 D0
TMP421
TMP422
TMP423
SBOS398C –JULY 2007–REVISED MAY 2012 www.ti.com
(1) Slave address 1001100 shown.
(2) Master should leave SDA high to terminate a two-byte read operation.
Figure 19. Two-Wire Timing Diagram for Two-Byte Read Format
HIGH-SPEED MODE to initiate a data transfer operation. The bus
continues to operate in Hs-mode until a STOP
In order for the two-wire bus to operate at frequencies
condition occurs on the bus. Upon receiving the
above 400kHz, the master device must issue a High-
STOP condition, the TMP421/22/23 switch the input
Speed mode (Hs-mode) master code (0000 1xxx) as
and output filters back to fast mode operation.
the first byte after a START condition to switch the
bus to high-speed operation. The TMP421/22/23 do
TIMEOUT FUNCTION
not acknowledge this byte, but switch the input filters
on SDA and SCL and the output filter on SDA to
The TMP421/22/23 reset the serial interface if either
operate in Hs-mode, allowing transfers at up to
SCL or SDA are held low for 30ms (typical) between
3.4MHz. After the Hs-mode master code has been
a START and STOP condition. If the TMP421/22/23
issued, the master transmits a two-wire slave address
are holding the bus low, the device releases the bus
and waits for a START condition. To avoid activating
the timeout function, it is necessary to maintain a
communication speed of at least 1kHz for the SCL
operating frequency.
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